EP0040702A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Authorization mechanism for transfer of program control or data between different address spaces having different storage protect keys
Assignee: International Business Machines Corp
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Filing: 1981-04-28
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Granted: —
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Expires: 2001-04-28
Abstract
Abstract An enhancement in a system/370 data processor permits one program in one address space to abtain access to data in another address space or to call a program in another address space without invoking a supervisor, with authorization to use a storage protect key other than that specifically assigned to the program by a supervisor program when in a new semi-privileged state. Programs executing in a particular address space have supervisor assigned storage protect key masks permitting the program, when authorized, to utilize a storage protect key other than the one specifically assigned by the supervisor. A second address space can be designated by a program, and when authorized, can cause transfer of data in main memory from one physical location to another associated with the different address space, and two different storage protect keys can be utilized. A calling program can provide addressability to data in its address space by combining storage protect key masks from the calling program with a key mask of a called program to permit access to data by the called program. Entering the called program causes the saving and changing of a problem/supervisor control bit and instruction address.
Inventors
- 👤 Andrew Robert Heller
- 👤 William Spencer Worley, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 21:01
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458; G06F12/1466; G06F12/1475
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
412 words
Data processing apparatus including a main memory and a processor capable of supporting a multiprogramming mode of operation, the main memory being comprised of addressable physical blocks of addressable storage locations and a protection mechanism based on addressable coded storage protect keys associated with the blocks and providing access control to the associated blocks, the contents of the main memory, in used, being, conventionally, data, problem programs, supervisor programs and supervisor established system control tables, such tables including address translation tables, the processor including processing and control circuitry, including control registers and a Program Status Word (PSW) register, to access decode and execute sequences of instructions from the main memory, the control registers including one (a first) addressing control register dedicated to storing the address of the currently to be used (primary) address translation table, the fields of the PSW register being decoded to include a plurality of control bits, such control bits including a problem program bit the state of which indicates the processor to be executing in problem or supervisor mode, a next instruction address field and a coded PSW protect key field to which the protection mechanism is responsive characterized in that (a) a second control register (CR3) is dedicated to storing a key mask (KM) comprising a plurality of bit positions equal in number to the number of possible combinations of bit states of the coded PSW protect key field (b) a third control register (CR5) is dedicated to storing the address of a supervisor established system control table, a linkage table, which table translates from the identity of a program to a characteristic set of parameters (ETE; Fig. 5) thereof, such parameters including an authority key mask (AKM bits 9-15) comprising a plurality of bit positions equal in number to the number of possible combinations of bit states of the coded PSW protect key field (c) the processing and control circuitry is arranged as a preliminary conditional function in the execution in problem mode of any instruction invoking a second program, to access the AKM of that second program via the linkage table and to test for compatibility in at least one bit position between the accessed AKM and the KM stored in the second control register whereby it is possible for an executing program to invoke the second program even though the second program is resident in a physical storage location to which the executing program is not granted access via the PSW protect key field.
Claim 2
Dependent Claim
412 words
Data processing apparatus including a main memory and a processor capable of supporting a multiprogramming mode of operation, the main memory being comprised of addressable physical blocks of addressable storage locations and a protection mechanism based on addressable coded storage protect keys associated with the blocks and providing access control to the associated blocks, the contents of the main memory, in used, being, conventionally, data, problem programs, supervisor programs and supervisor established system control tables, such tables including address translation tables, the processor including processing and control circuitry, including control registers and a Program Status Word (PSW) register, to access decode and execute sequences of instructions from the main memory, the control registers including one (a first) addressing control register dedicated to storing the address of the currently to be used (primary) address translation table, the fields of the PSW register being decoded to include a plurality of control bits, such control bits including a problem program bit the state of which indicates the processor to be executing in problem or supervisor mode, a next instruction address field and a coded PSW protect key field to which the protection mechanism is responsive characterized in that (a) a second control register (CR3) is dedicated to storing a key mask (KM) comprising a plurality of bit positions equal in number to the number of possible combinations of bit states of the coded PSW protect key field (b) a third control register (CR5) is dedicated to storing the address of a supervisor established system control table, a linkage table, which table translates from the identity of a program to a characteristic set of parameters (ETE; Fig. 5) thereof, such parameters including an authority key mask (AKM bits 9-15) comprising a plurality of bit positions equal in number to the number of possible combinations of bit states of the coded PSW protect key field (c) the processing and control circuitry is arranged as a preliminary conditional function in the execution in problem mode of any instruction invoking a second program, to access the AKM of that second program via the linkage table and to test for compatibility in at least one bit position between the accessed AKM and the KM stored in the second control register whereby it is possible for an executing program to invoke the second program even though the second program is resident in a physical storage location to which the executing program is not granted access via the PSW protect key field.
Claim 3
Dependent Claim
110 words
Apparatus as claimed in claim 1 wherein the invoked program parameters include a (new) problem program bit, an entry key mask (EKM bits 96-lll) and an instruction address (EIA bits 40-62) and the processing and control circuitry is arranged, when further execution of an instruction invoking a second program is permitted, to save (in the general registers GRO-15), the key mask from the second register and the problem program bit and the next instruction address from the PSW register and to write into the second control register and the PSW register, respectively, the OR function of the transferred KM and the EKM, and new problem program bit and the EIA.
Claim 4
Dependent Claim
95 words
Apparatus as claimed in claim 2 wherein the processing and control circuitry is arranged to decode and execute, in problem mode, a program transfer instruction transferring execution from the second program to the program which invoked it, such execution including testing the saved problem program bit against the problem program bit in the PSW register and signalling an error when they are not of the same state and forming the AND function of the saved EKM and the KM resident in the second control register and storing the AND function in the second control register.
Claim 5
Dependent Claim
51 words
Apparatus as claimed in any preceding claim wherein a third control register (CRO) includes a bit position (position 4) under the exclusive control of the supervisor program, the bit state of which, enables or disables access by an instruction executing in problem mode under authority of the corresponding key mask pair.
Claim 6
Dependent Claim
113 words
Apparatus as claimed in any one of claims 1 to 3 wherein a third control register (CRO) includes a bit position (position 4) under the exclusive control of the supervisor program, the processing and control circuitry being arranged to decode and execute in problem mode instructions transferring data between two physical blocks of main memory and as a preliminary conditional function in the execution of which, being arranged to test the bit state of said bit position and, for one bit state thereof, to condition the protection mechanism to respond to the coded PSW protect key field in respect of one block and the key mask pair in respect of the other block.
References Cited (Backward Citations)
No citation records indexed.
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