EP0040001A2
Expired / Lapsed
EP
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A dynamic semiconductor memory device with decreased clocks
Assignee: Fujitsu Ltd
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Filing: 1981-04-13
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Granted: —
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Expires: 2001-04-13
Abstract
Abstract Disclosed is a dynamic semiconductor memory device with decreased clocks having a pull up circuit (P o , P 1 ) associated with a pair of bit lines (BL, BL'). The pull up circuit (P o , P i ) comprises a pair of first switching transistors (Q 51, Q 61 ) connected between a power supply line (Vcc) and the associated bit line (BL, BL'), and, a pair of second switching transistors (Q 10 ,Q 11 )0 Each gate of the second switching transistors (Q 10 Q 11 ) is connected to the bit line of opposite side (BL', BL). The turning on or off of the second switching transistor(Q 10 ,Q 11 ) controls the gate potential of the first switching transistor (Q 51 , Q 61 ).
Inventors
- 👤 Yoshihiro Takemae
- 👤 Shigeki Nozaki
- 👤 Tsutomu Mezawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 13:28
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4094; G11C7/00; G11C7/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
138 words
A dynamic semiconductor memory device comprising: a plurality of dynamic memory cells arranged in a matrix; a sense amplifier associated with a pair of bit lines; and; a pull up circuit associated with each of said pair of bit lines for charging up the associated bit lines; characterized in that; said pull up circuit comprises: a pair of first switching transistors respectively connected between a power supply line and the associated bit lines, for charging up said bit lines; and; a pair of second switching transistors respectively connected between the gates of said pair of first switching transistors and the ground side of said sense amplifier, for respectively controlling the gate potentials of said pair of first switching transistors, each gate of said pair of second switching transistors being connected to the bit line of the opposite side.
Claim 2
Dependent Claim
138 words
A dynamic semiconductor memory device comprising: a plurality of dynamic memory cells arranged in a matrix; a sense amplifier associated with a pair of bit lines; and; a pull up circuit associated with each of said pair of bit lines for charging up the associated bit lines; characterized in that; said pull up circuit comprises: a pair of first switching transistors respectively connected between a power supply line and the associated bit lines, for charging up said bit lines; and; a pair of second switching transistors respectively connected between the gates of said pair of first switching transistors and the ground side of said sense amplifier, for respectively controlling the gate potentials of said pair of first switching transistors, each gate of said pair of second switching transistors being connected to the bit line of the opposite side.
Claim 3
Dependent Claim
135 words
A dynamic semiconductor memory device comprising: a plurality of dynamic memory cells arranged in a matrix; a sense amplifier associated with a pair of bit lines; and; a pull up circuit associated with each of said pair of bit lines for charging up the associated bit lines; characterized in that; said pull up circuit comprises: a pair of first switching transistors respectively connected between a power supply line and the associated bit lines, for charging up said bit lines; and; a pair of second switching transistors respectively connected between the gates of said pair of first switching transistors and the associated bit lines, for respectively controlling the gate potentials of said pair of first switching transistors, each gate of said pair of second switching transistors being connected to the bit line of the opposite side.
Claim 4
Dependent Claim
135 words
A dynamic semiconductor memory device comprising: a plurality of dynamic memory cells arranged in a matrix; a sense amplifier associated with a pair of bit lines; and; a pull up circuit associated with each of said pair of bit lines for charging up the associated bit lines; characterized in that; said pull up circuit comprises: a pair of first switching transistors respectively connected between a power supply line and the associated bit lines, for charging up said bit lines; and; a pair of second switching transistors respectively connected between the gates of said pair of first switching transistors and the associated bit lines, for respectively controlling the gate potentials of said pair of first switching transistors, each gate of said pair of second switching transistors being connected to the bit line of the opposite side.
Claim 5
Dependent Claim
60 words
A dynamic semiconductor memory device as claimed in Claim 1 or 2, wherein, said pull up circuit further comprises a pair of capacitors having first and second electrodes, each of said first electrodes being connected to the gate of one of said pair of first switching transistors, and each of said second electrodes being adapted to receive a clock signal.
Claim 6
Dependent Claim
68 words
A dynamic semiconductor memory device as claimed in Claim 3, wherein, one of said first switching transistors connected to one bit line, and one of said second switching transistors, the gate of which is connected to the other bit line, said first and second switching transistors are adapted to be turned on and off, respectively, for charging up the associated bit line, when said clock signal is fed.
References Cited (Backward Citations)
No citation records indexed.
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