Semiconductor integrated circuit device

Claim 2

A semiconductor integrated circuit device comprising a semiconductor logic circuit operable both in active and standby modes and a self-sub-bias generating means for providing predetermined self-sub-bias voltages to said semiconductor logic circuit, characterized in that said self-sub-bias generating means includes a first generator (2-2) for providing a first self-sub-bias voltage at the time of the active mode and a second generator (2-4) for providing a second self-sub-bias voltage different from the first mode at the time of the standby mode.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein said self-sub-bias generating means includes a first generator (2-2) for generating a first self-sub-bias voltage at the time of said active mode and a second generator (2-4) for generating self-sub-bias voltage at the time of said standby mode.

Claim 4

A semiconductor integrated circuit device according to claim 1, wherein said semiconductor logic circuit is a MOS inverter including a mode switching transistor (T6) having the gate for receiving a chip enable signal (CE) and the current path connected between a power supply terminal (V DD ) and a node (3-7), a load element (T5, Rl) connected between said node (3-7) and an output terminal (3-6), and a transistor (T4) having the gate receiving an input signal and connected between said output terminal (3-6) and ground.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein said load element is a load MOS transistor (T5).

Claim 6

A semiconductor integrated circuit device according to claim 3, wherein said load element is a resistor (Rl).

Claim 7

A semiconductor integrated circuit device according to claim 2, wherein the frequency of said second self-sub-bias voltage generated from said second generator (2-4) is set to a value within a range from 1/10 to 1/100 of the frequency of the first self-sub-bias voltage generated from said first generator (2-2).

Claim 8

A semiconductor integrated circuit device according to claim 2, wherein said first generator (2-2) includes an oscillator (4-A), an amplifier (4- B ) for amplifying the output of said oscillator (4-A) and a charge pump circuit (4-C) having a construction consisting of at least one stage for imparting the output of said amplifier (4-B) with a predetermined level.

Claim 9

A semiconductor integrated circuit device according to claim 2, wherein said second generator (2-4) includes an oscillator (5-A), an amplifier (5- B ) for amplifying the output of said oscillator circuit (5-A), and a charge pump circuit (5-C) having a construction consisting of a plurality of stages for increasing the bias voltage level of the output signal from said amplifier (5-B).

Claim 10

A semiconductor integrated circuit device according to claim 3, wherein said mode switching transistor (T6) functions as an I-type or D-type MOS transistor for causing sufficient current with a first back gate bias given in said active mode and functions as a perfect E-type MOS transistor for perfectly cutting off current with a second back gate bias given in said standby mode.

Claim 11

A semiconductor integrated circuit device according to claim 3, wherein the threshold voltage of said mode switching transistor (T6) is substantially zero volt determined by the back gate bias voltage in the active mode and suddenly increases with a voltage less than the back gate bias that is given in the standby mode.

Claim 12

A semiconductor integrated circuit device according to claim 10, wherein the impurity concentration of the portion of the semiconductor substrate on which said mode switching transistor ( T 6) is made suddenly increases at a depth intermediate between the bottom of a depletion layer formed with the first self-sub-bias given in the active mode and the bottom of a depletion layer formed with the second self-sub-bias given in the standby mode.

Claim 13

A semiconductor integrated circuit device comprising an integrated circuit including first and second MOS inverters each including a load resistor provided between a first voltage supply terminal and an output terminal and a drive element provided between a second voltage supply terminal and said output terminal, the output terminal of said first MOS inverter being connected to the gate electrode of the drive element in said second MOS inverter, the output terminal of said second MOS inverter being connected to the gate electrode of the drive element in said first MOS inverter, a transfer element being connected to the output terminal of each of said first and second MOS transistors, and bias voltage generating means for generating a first self-sub-bias voltage with respect to the semiconductor substrate of said integrated circuit in a first mode and a second self-sub-bias voltage in a second mode.

Claim 14

A semiconductor integrated circuit device comprising an integrated circuit including first and second MOS inverters each including a load resistor provided between a first voltage supply terminal and an output terminal and a drive element provided between a second voltage supply terminal and said output terminal, the output terminal of said first MOS inverter being connected to the gate electrode of the drive element in said second MOS inverter, the output terminal of said second MOS inverter being connected to the gate electrode of the drive element in said first MOS inverter, a transfer element being connected to the output terminal of each of said first and second MOS transistors, and bias voltage generating means for generating a first self-sub-bias voltage with respect to the semiconductor substrate of said integrated circuit in a first mode and a second self-sub-bias voltage in a second mode.