Data processing system

Claim 2

A data processing system comprising central processor means responding to macro-instructions to produce microcontrol signals and including arithmetic-logic means responsive to selected ones of the microcontrol signals for performing arithmetic or logical operations, and memory means for storing information for use in the data processing system, characterised by instruction processor means (12) for decoding macro-instructions to produce a starting address of one or more micro-instructions; micro-sequencing means (13) responsive to said starting address for providing a sequence of one or more micro-instructions for producing a plurality of said microcontrol signals, address translation. means (14) responsive to selected ones of said microcontrol signals for converting logical addresses into physical addresses; and in that said memory means include main memory means (16) for storing said information; temporary storage means (17) for storing a selected portion of said information and having at least one set of input and output ports; controller means (18) interconnected between said main memory means and said temporary storage means for controlling the transfer of information between said main memory means and said temporary storage means; and first means (19, 20) for interconnecting said at least one set (17A) of input and output ports with said instruction processor means (12), said arithmetic logic means (11) and said address translation means (14) for transferring information therebetween.

Claim 3

A data processing system in accordance with claim 1, characterised in that said first interconnecting means (19, 20) includes a first address bus (19) for transferring address information; and a first data bus (20) for transferring non-address information.

Claim 4

A data processing system in accordance with claim 1 or 2, characterised in that said temporary storage means (19) includes another set (17B) of input and output ports, and by an input/output channel means (23) for communicating with one or more input/output devices external to said data processing system; and second means (21, 22) for interconnecting said another set (17B) of input and output ports with said input/output channel means for transferring information therebetween.

Claim 5

A data processing system in accordance with claim 3, characterised in that said second interconnecting means (21, 22) comprises a second address bus (21) for transferring address information; and a second data bus (22) for transferring non-address information.

Claim 6

A data processing system in accordance with claim 4, characterised by a further data bus (25) interconnecting said instruction processor means (12), said arithmetic logic means (11), said microsequencing means (13), said address translation unit (14) and said input/output channel means (23) for transferring non-address information among said interconnected means; logical address bus means (25) interconnecting said instruction processor means (12), said arithmetic logic means (11), said microsequencing means (13), said address translation unit (14) and said input/output channel means (23) for transferring logical address information among said interconnected means; and physical address bus means (27) interconnecting said instruction processor means (12), said arithmetic logic means (11), said microsequencing means (13), said address translation unit (14) and said input/output channel means (23) for transferring physical address information among said interconnected means.

Claim 7

A data processing system in accordance with claim 5, characterised by means for controlling the transfer of information at said one and said another sets of input and output ports of said temporary storage means so that said first interconnecting means provides for transfer of information at said one set of ports during a first portion of an operating time cycle of said data processing system and for transfer of information at said another set of ports during a second portion of said operating time cycle (Fig 40).

Claim 8

A data processing system which utilizes first logical addresses containing a first number of address bits and second .logical addresses containing a second number of address bits, the system comprising means for providing a plurality of instruction words a first plurality of which require the use of said first logical addresses and a second plurality of which require the use of said second logical addresses, said instruction words each including one or more selected bits for identifying the logical addresses used by said instruction words as being either said first logical addresses or said second logical addresses; decode means- responsive to said instruction words, for decoding said instruction words, the decoding thereof producing address descriptor bits, one or more selected ones of said address descriptor bits signifying which type of logical address is required by the decoded instruction; means for converting logical addresses signified as first logical addresses having said first number of bits into logical addresses containing said second number of bits; and means for translating said converted logical addresses or for translating said second logical addresses into physical addresses containing said second number of address bits.

Claim 9

A data processing system which utilizes first logical addresses containing a first number of address bits and second .logical addresses containing a second number of address bits, the system comprising means for providing a plurality of instruction words a first plurality of which require the use of said first logical addresses and a second plurality of which require the use of said second logical addresses, said instruction words each including one or more selected bits for identifying the logical addresses used by said instruction words as being either said first logical addresses or said second logical addresses; decode means- responsive to said instruction words, for decoding said instruction words, the decoding thereof producing address descriptor bits, one or more selected ones of said address descriptor bits signifying which type of logical address is required by the decoded instruction; means for converting logical addresses signified as first logical addresses having said first number of bits into logical addresses containing said second number of bits; and means for translating said converted logical addresses or for translating said second logical addresses into physical addresses containing said second number of address bits.

Claim 10

A system in accordance with claim 7 wherein said first logical addresses have fewer bits than said second logical addresses.

Claim 11

A system in accordance with claim 8 wherein said first logical addresses are logical word addresses which have fifteen bits and said second logical addresses are logical word addresses which have thirty-one bits.

Claim 12

A system in accordance with claim 8 wherein said first logical addresses are logical byte addresses which have sixteen bits and said second logical addresses are logical byte addresses which have thirty-two bits.

Claim 13

A system in accordance with claim 7, 8, 9 or 10 wherein said decode means comprises programmable read-only-memory means.

Claim 14

A system in accordance with claim 11 wherein said programmable read-only-memory means includes a first logic means responsive to said one or more selected bits for decoding only instruction words which use said first logical addresses; and a second logic means responsive to said one or more selected bits for decoding only instruction words which use said second logical addresses, said first and second logic means being arranged to operate simultaneously in response to said instruction words for decoding said first plurality of instruction words and said second plurality of instruction words on a non-mutually exclusive basis.

Claim 15

A system in accordance with claim 12 wherein said address translation means includes translation storage means capable of storing first memory allocation data for determining physical addresses in response to said converted first logical addresses and further capable of storing second memory allocation data for determining physical addresses in response to either said converted first logical addresses or said second logical addresses; means for selectively supplying said first memory allocation data or said second memory allocation data to said translation storage means, said selectively stored memory allocation data responding to corresponding converted first logical addresses or second logical addresses to produce said physical addresses.

Claim 16

A system in accordance with claim 13 and further including means responsive to at least one bit of said converted first logical addresses or said second logical addresses for identifying whether the address to which said translation storage means responds is a first logical address or a second logical address.

Claim 17

A system in accordance with claim 13 and further including means for determining whether said first memory allocation data or said second memory allocation data is to be used to produce said phusical addresses.

Claim 18

A system in accordance with claim 13 wherein logical addresses to be used in said system are grouped in blocks thereof, each logical address including a plurality of tag bits for identifying in which block the logical address belongs and said translation storage means stores selected memory allocation data for use in translating selected blocks of logical addresses into physical addresses, said system further including tag storage means for storing the tag bits of the selected blocks of logical addresses which correspond.to the memory allocation data stored in said translation storage means; and means for comparing the tag bits of logical addresses stored in said tag storage means with the tag bits of an input logical address to be supplied to said translation storage means for translation thereof into a physical address for identifying whether said input logical address corresponds to a logical address of one of said selected blocks thereof.

Claim 19

A system in accordance with claim 16 wherein the system includes memory means for storing a plurality of page tables each of which contain memory allocation data for use in translating one or more selected blocks of logical addresses; means responsive to an indication from said comparing means that the memory allocation data for translating said input logical address is not available in said. translation storage means for accessing new memory allocation data capable'of translating said input logical address from said page tables, in said memory means; and means for replacing memory allocation data currently stored in said translation storage means with said new accessed memory allocation data.

Claim 20

A system in accordance with claim 17 and further including means for indicating a page table fault if the page table required to be accessed from said memory means is not resident therein.

Claim 21

A system in accordance with claim 17 wherein the memory allocation data to be accessed from a page table in said memory means can be accessed directly as a one-level page table access or can be accessed indirectly via an intermediate page table as a two-level page table access; and further including means for determining whether said accessing is a one-level page table access or a two-level page table access.

Claim 22

A system in accordance with claim 19 wherein said system includes means for providing a one-level page table access in response to an input logical address, said means comprising means responsive to a selected field of said input logical address for obtaining a first address identifying the starting address of a selected page table in said memory means; means responsive to another selected field of said input logical address representing a selected offset from the starting address of said selected page table to provide a page table entry address at said offset; and means for extracting a selected field of said page table entry address requesting the memory allocation data for said input logical address and for placing said memory allocation data in said translation storage means.

Claim 23

A system in accordance with claim 17 wherein said system includes means for providing a two-level page table access in response to an input logical address, said means comprising means responsive to a selected field of said input logical address for obtaining a first address identifying the starting address of a first selected page table in said memory means; means responsive to another selected field of said input logical address representing a first selected offset from the starting address of said first selected page table to provide a first page table entry address at said first offset; means responsive to a selected field of said first page table entry address for obtaining a second address identifying the starting address of a second selected page table in said memory means; means responsive to still another field of said input logical address representing a second selected offset from the starting address of said second selected page table to provide a second page table entry address at said second offset; and means for extracting a selected field of said second page table entry address representing the memory allocation data for said input logical address and for placing said memory allocation data in said translation storage means.

Claim 24

A system in accordance with claim 19 wherein the bits of a further selected field of said input logical address are all zero when a one-level page table access is required for said input logical address; and means for indicating a further page table fault when said one-level or two-level page table determining means determines that said page table access is a one-level access and said further selected field of said input logical address includes one or more non-zero bits.

Claim 25

A data processing system which utilizes memory storage means for storing a plurality of different groups of data, said memory storage means being capable of storing said different groups of data at different designated locations thereof, said designated locations being identifiable as storage segment locations having a descending order of protection with respect to data reference accesses by an operator, the addresses of data in each group thereof having a plurality of selected segment bits which identify the storage segment location in which said data is stored, said system comprising means for responding to said selected segment bits of an address which identify the storage segment location at which a data reference access is requested to compare said selected segment bits with a plurality of previously selected segment bits which identify the storage segment location at which a requested data reference access has already been provided with respect to a preceding address; and means responsive to said comparing means for prohibiting a data reference access to an address at a storage segment location which said selected segment bits identify as a segment location having a lower order of protection than the segment location identified by said previously selected segment bits.

Claim 26

A data processing system which utilizes memory storage means for storing a plurality of different groups of data, said memory storage means being capable of storing said different groups of data at different designated locations thereof, said designated locations being identifiable as storage segment locations having a descending order of protection with respect to data reference accesses by an operator, the addresses of data in each group thereof having a plurality of selected segment bits which identify the storage segment location in which said data is stored, said system comprising means for responding to said selected segment bits of an address which identify the storage segment location at which a data reference access is requested to compare said selected segment bits with a plurality of previously selected segment bits which identify the storage segment location at which a requested data reference access has already been provided with respect to a preceding address; and means responsive to said comparing means for prohibiting a data reference access to an address at a storage segment location which said selected segment bits identify as a segment location having a lower order of protection than the segment location identified by said previously selected segment bits.

Claim 27

A system in accordance with claim 23 wherein said comparing means includes means for providing a plurality of selected segment bits which correspond to the selected segment bits of an accessed address which identify the storage segment in which the data reference corresponding to said accessed address is stored; means responsive to the segment bits of an accessed address and to the segment bits of the next address to be accessed to determine the order of protection of the storage segment of said next address relative to the previously accessed address to provide a segment control signal when said next address corresponds to a data reference stored in a sotrage segment location having a lower order of protection than the storage segment location of a data reference at the previously accessed address.

Claim 28

A system in accordance with claim 24 wherein said data reference access prohibiting means includes means responsive to said segment control signal for producing a coded error protection signal which indicates that the data reference at said next address is in a storage segment location which is prohibited from access; and means responsive to said coded error signal for producing a coded fault signal identifying that a specified fault has occurred due to the presence of said coded error protection signal.

Claim 29

A system in accordance with claim 23 and further including means for providing access to data references in a current storage segment; means for providing program control instructions which call for access to.subroutines stored in a storage segment location different from the storage location currently being used for data references; means responsive to said program control instructions for determining whether a specified called storage segment in which a subroutine is located has a higher order of protection than said current storage segment; and means further responsive to said program control instruction when said called storage segment has said higher order of protection for providing entry into said called storage segment and access to a subroutine therein..

Claim 30

A system in accordance with claim 26 and further including means for indicating a subroutine call fault condition when said called storage segment has a lower order of protection than said current storage segment.

Claim 31

A system in accordance with claim 26 and further including means for providing a program control instruction which requires a return from operation with respect to a called storage segment to operation with respect to a previously used current storage segment; means for determining whether said previously used current storage segment has a lower order of protection than said called storage segment; and means responsive to a return address in said previously used current storage segment for providing access to said return address when said previously used current storage segment has said lower order of protection.

Claim 32

A system in accordance with claim 28 and further including means for indicating a return fault condition when said previously used current storage segment has a higher order of protection than said called storage segment.

Claim 33

A system in accordance with claim 26 wherein said entry providing means includes means responsive to said program control instruction to provide a branch address including a first field identifying the called storage segment and a second field specifying a coded gate number; said called storage segment having a storage location which identifies an array of gate numbers resident in said called storage segment; means for comparing the coded gate numbers of said branch address with the maximum gate number resident in said called storage segment; means for permitting said entry into said called storage segment and access to the subroutine therein when said coded gate number is 'determined to be less than said maximum gate number.

Claim 34

A system in accordance with claim 30 and further including means for indicating a call fault condition when said coded gate number is determined to be equal to or greater than said maximum gate number.

Claim 35

A data processing system having a memory system, said memory system comprising a main memory storage means capable of storing a first plurality of blocks of data words; an intermediate cache storage means capable of storing a second plurality of blocks of data words corresponding to a selected number of said first plurality of blocks of data words stored in said main memory storage means; and control means connected between said main memory storage means and said intermediate cache storage means for controlling the transfer of blocks of data words between said main memory storage means and said intermediate cahce storage means.

Claim 36

A data processing system having a memory system, said memory system comprising a main memory storage means capable of storing a first plurality of blocks of data words; an intermediate cache storage means capable of storing a second plurality of blocks of data words corresponding to a selected number of said first plurality of blocks of data words stored in said main memory storage means; and control means connected between said main memory storage means and said intermediate cache storage means for controlling the transfer of blocks of data words between said main memory storage means and said intermediate cahce storage means.

Claim 37

A data processing system in accordance with claim 32 wherein said intermediate cache storage means is capable of accepting an address which includes a first plurality of tag bits, a second plurality of index bits, and a third plurality of word pointer bits; and further including tag store means for storing a block of tag bits combinations, each combination identifying one of the second plurality of blocks of data words stored in said intermediate cahce storage means which correspond to said selected number of said first plurality of blocks of data words in said main memory storage means; and tag identifying means responsive to the gat bits of an incoming address signal which is supplied to said intermediate cache storage means for comparing the tag bits of said incoming address to the tag bit combinations stored in said tag store means for supplying a tag comparison signal which signifies whether or not said incoming address corresponds to an address in the plurality of blocks of data words stored in said intermediate cache means.

Claim 38

A system in accordance with claim 33 and further including means responsive to said tag comparison signal for indicating a cache fault condition if the tag bits of said incoming address do not so correspond and for indicating a cache operate condition if the tag bits of said incoming address do so correspond.

Claim 39

A system in accordance with claim 34 and further including index identifying means responsive to the index bits of an incoming address for identifying a selected one of said second plurality of blocks of data words stored in said intermediate cache storage means.

Claim 40

A system in accordance with claim 35 and further including word identifying means responsive to the word pointer bits of an incoming address for identifying the location of a selected one of the data words in said selected one of said second plurality of blocks of data words stored in said intermediate cache storage means; and means for accessing the selected one of data words in said intermediate cache storage means when said tag comparison signal indicates a cache operate condition.

Claim 41

A system in accordance with claim 26 wherein said tag identifying means, said index identifying means, said word identifying means, and said accessing means are arranged to permit the overlapping of the identification and accessing operations with respect to a data word with the identification and accessing operations with respect to a successive data word.

Claim 42

A system in accordance with claim 37 and further including means for providing a direct data transmission path for transferring a block of data words directly to said main memory storage means via said control means without storing said directly transferred block of data words in said intermediate cache storage means.

Claim 43

A data processing system in accordance with claim 32 wherein said control means includes means for transferring blocks of data words in sequence from said main memory storage means to said intermediate cache storage means, each block of data words having a selected number of data words therein; means for detecting all single-bit errors in the selected number of data words of a block thereof which is being so transferred prior to the correction of any of said detected single-bit errors; and means for correcting all single-bit errors in said selected number of data words of said block thereof which is being so transferred prior to detecting single-bit errors in a subsequent block of data words which is to be subsequently transferred.

Claim 44

A data processing system in accordance with claim 32 wherein said intermediate cache storage means includes first address and data ports providing access to said intermediate cache storage means by first selected data request sources during an operating time cycle of said data processing system; and second address and data ports providing access to said intermediate cache storage means by second selected data request sources during an operating time cycle of said data processing system.

Claim 45

A data processing system in accordance with claim 40 and further including means for enabling said first address and data ports for providing access to said intermediate cache storage means by a first selected data request source only during a first portion of any data processing operating time cycle and for enabling said second address and data ports for providing access to said intermediate cache storage means by a second selected data request source only during a second portion of any data processor operating time cycle.

Claim 46

A data processing system in accordance with claim 32 wherein said intermediate cache storage myans is arranged to store portions of data words within successive bounded locations within said intermediate cache storage means, said stored data words being capable of having a portion thereof stored in a first bounded location and the remaining portion thereof in a second subsequent bounded - ocation of said intermediate cache storage means so that when said data word is accessed from said intermediate cache storage means the location of said data word portions which form said accessed data word are incorrect; and means for rotating the locations of said data word portions for said incorrectly formed accessed words so that the accessed data word is correctly formed, said rotating means performing the rotating of said locations without interrupting the overall data word accessing operation.

Claim 47

A data processing system having one or more processor units and a memory interface control means, and a memory system comprising one or more memory modules for storing data, the location of the data bits of said data being identified by a row and column designation for each such module; means responsive to a select control signal from said interface control means, said select control signal identifying a selected module of said one or more memory modules; means responsive to a row control signal from said interfact control means, said row control signal identifying a row of said selected memory module; and means responsive to a column control signal from said interface control means, said column control signal identifying a column of said selected module.

Claim 48

A data processing system having one or more processor units and a memory interface control means, and a memory system comprising one or more memory modules for storing data, the location of the data bits of said data being identified by a row and column designation for each such module; means responsive to a select control signal from said interface control means, said select control signal identifying a selected module of said one or more memory modules; means responsive to a row control signal from said interfact control means, said row control signal identifying a row of said selected memory module; and means responsive to a column control signal from said interface control means, said column control signal identifying a column of said selected module.

Claim 49

A data processing system in accordance with claim 43 said memory system further including means responsive to a load control signal from said interface control means, said load control signal controlling the loading of data being ; supplied for storage into said selected memory module; and means responsive to an access control signal from said interface control system, said access control signal controlling the supplying of data which is being accessed from storage in said selected memory module.

Claim 50

A data processing system in accordance with claim 43 or 44 said memory system further including means responsive to a refresh control signal from said interface control system, said refresh control signal controlling the refreshing of data which is stored in said selected module.

Claim 51

A data processing system in accordance with claim 45 and further wherein each of said memory modules includes a memory array which comprises a plurality of memory storage planes for storing data; means responsive to said select, row, column, load and access control signals for providing row and column addresses in sequence for data in each of said memory storage planes whereby data can be stored or accessed in sequence in to or from, respectively, said plurality of memory storage planes.

Claim 52

A data processing system in accordance with claim 46 where said row and column address providing means include a plurality of latch and driver logic means; and time means for providing operation of said latch and driver logic means in a selected sequence.

Claim 53

A data processing system capable of handling a first plurality of instructions forming a first designated basic set thereof and a plurality of second instructions forming a second designated extended set thereof, each of said first or second instructions including an operating code portion thereof and being capable of including at least one displacement portion thereof, said system including instruction processor means comprising instruction decode register means having at least two register regions, a first of said regions designated to temporarily store said operating code portion of an instruction and said at least one other region designated to temporarily store said at least one displacement portion; instruction decode shifter means responsive to an incoming instruction of said basic instruction set or said extended instruction set for entering said instruction into said instruction decode register means so that the operating code portion thereof is temporarily stored in said first designated region and said at least one displacement portion, if included, is temporarily stored in said at least one other designated region.

Claim 54

A data processing system capable of handling a first plurality of instructions forming a first designated basic set thereof and a plurality of second instructions forming a second designated extended set thereof, each of said first or second instructions including an operating code portion thereof and being capable of including at least one displacement portion thereof, said system including instruction processor means comprising instruction decode register means having at least two register regions, a first of said regions designated to temporarily store said operating code portion of an instruction and said at least one other region designated to temporarily store said at least one displacement portion; instruction decode shifter means responsive to an incoming instruction of said basic instruction set or said extended instruction set for entering said instruction into said instruction decode register means so that the operating code portion thereof is temporarily stored in said first designated region and said at least one displacement portion, if included, is temporarily stored in said at least one other designated region.

Claim 55

A data processing system in accordance with claim 48 said instruction processor means further including instruction decoding means for decoding the operating code portion of an instruction supplied thereto from said instruction decode -register means to produce a plurality of operating code descriptors associated with said decoded instructions and for producing a starting address of one or more microinstructions associated with said decoded instruction.

Claim 56

A data processing system in accordance with claim 49 and further including displacement handling means responsive to a displacement portion of an instruction, if any, supplied thereto from said instruction decode register means to provide displacement data to said data processing system.

Claim 57

A data processing system in accordance with claim 50 wherein said displacement handling means includes sign extend logic means for extending the displacement portion of:an instruction supplied thereto by sign extended data, if.necessary.

Claim 58

A data processing system in accordance with claim 50 or 51 wherein said displacement handling means includes zero extend logic means for extending the displacement portion of an instruction supplied thereto by a selected number of zero bits, if necessary.

Claim 59

A data processing system in accordance with claim 52 wherein said displacement handling means includes ones extend logic means for extending the displacement portion of an instruction supplied thereto by a selected number of one bits, if necessary.

Claim 60

A data processing system in accoreance with claim 53 wherein said displacement handling means further includes means responsive to said displacement data for supplying said data in the form of a logical address to provide a memory reference for said system.

Claim 61

A data processing system in accordance with claim 48 or 49 and further including instruction cache storage means for storing a plurality of instructions; means for identifying when a requested instruction is stored in said instruction cache storage means; said instruction cache storage means being responsive to the address of a requested instruction stored therein when said identifying means indicates that said requested instruction is stored in said instruction cache storage means for supplying said requested instruction to said instruction decode shifter means.

Claim 62

A data processing system in accordance with claim 55 and further including -means for accessing said requested instruction from a -main memory storage means when said identifying means indicates that said requested instruction is not stored in said instruction cache storage means.

Claim 63

A data processing system in accordance with claim 56 and further including means for providing a direct transmission path to said instruction decode shifter means for a requested instruction which has been accessed from said main memory storage means.

Claim 64

A data processing system in accordance with claim 48 or 49 wherein said instruction decoding means is an array of programmable read-only-memories.

Claim 65

A data processing system in accordance with claim 58 wherein said instruction decoding means includes first programmable read-only-memory means for decoding instructions of said basic instruction set and second programmable read-only-memory means for decoding instructions of said extended instruction set.

Claim 66

A data processing system in accordance with claim 59 wherein each of said instructions to be decoded have selected bit code combinations for,identifying whether said instruction is from said basic instruction set or from said extended instruction set and further including means for examining the selected bit code combination of an instruction to be decoded to determine whether said instruction is from said basic instruction set or from said extended instruction set; and means responsive to said selected bit code combination for enabling a selected one of said first or second programmable read-only-memory means to decode said instruction depending on whether the instruction to be decoded is from said basic instruction set or from said extended instruction set.

Claim 67

A data processing system in accordance with claim 60 wherein said selected bit code combination comprises a 1 in bit ⌀ and 1001 in bits 12-15 of said instruction for selected instructions from said extended instruction set.

Claim 68

A data processing system in accordance with claim 60 wherein said selected bit code combination comprises a 1 in bit 0 and 011000 in bits 10-15 of said instruction for other selected instructions from said extended instruction set.

Claim 69

A data processing system in accordance with claim 60 wherein said selected bit code combination comprises a 1 in bit ⌀, a 0 in bit 5 and 111000 in bits 10-15 of said instruction for still other selection instructions from said extended instruction set.

Claim 70

A data processing system in accordance with claim 60 wherein said selected bit code combination comprises 0 in bit 5 and 1000 in bits 12-15 of said instruction for selected instructions from said basic instruction set.

Claim 71

A data processing system having a central processor responsive to macro-instructions for determining starting microaddresses of micro-instructions, and a microsequencing means for providing one or more successive micro-instructions for use by said central processor, said microsequencing means comprising microcontrol store means for storing a plurality of micro- instructions; means for decoding said macro-instructions to produce a starting microaddress of one of said micro-instructions; said microcontrol store means being responsive to said starting microaddress for accessing a current micro-instruction stored at said microaddress of said microcontrol store means; micro- instruction decoding means responsive to selected bits of said currently accessed micro-instruction for determining the micro- address of the next successive micro-instruction; a plurality of microaddress sources capable of supplying the microaddress of the next successive micro-instruction; and means responsive to said microaddress determining means for selecting the microaddress of the next micro-instruction from one of said microaddress sources.

Claim 72

A data processing system having a central processor responsive to macro-instructions for determining starting microaddresses of micro-instructions, and a microsequencing means for providing one or more successive micro-instructions for use by said central processor, said microsequencing means comprising microcontrol store means for storing a plurality of micro- instructions; means for decoding said macro-instructions to produce a starting microaddress of one of said micro-instructions; said microcontrol store means being responsive to said starting microaddress for accessing a current micro-instruction stored at said microaddress of said microcontrol store means; micro- instruction decoding means responsive to selected bits of said currently accessed micro-instruction for determining the micro- address of the next successive micro-instruction; a plurality of microaddress sources capable of supplying the microaddress of the next successive micro-instruction; and means responsive to said microaddress determining means for selecting the microaddress of the next micro-instruction from one of said microaddress sources.

Claim 73

A data processing system in accordance with claim 65 wherein said plurality of microaddress sources includes microprogram counter means capable of providing the microaddress of the next successive micro-instruction stored in said microcontrol store means, said next successive microaddress being made available to said microaddress selecting means from said microprogram counter means.

Claim 74

A data processing system in accordance with claim 65 or 66 wherein said plurality of microaddress sources includes stack storage means for storing a plurality of microaddresses of micro-instructions stored in said microcontrol store means, the last stored microaddress in said stack storage means being made available to said microaddress selecting means from said stack storage means.

Claim 75

A data processing system in accordance with claim 67 wherein said plurality of microaddress sources includes micro- address forming means responsive to selected bits derived from said currently accessed micro-instruction and to selected bits received from sources external to said microsequencing means capable of forming a plurality of concatenated microaddresses; and means for selecting one of said plurality of concatenated microaddresses, said selected concatenated microaddress being made available to said microaddress selecting means.

Claim 76

A data processing system in accordance with claim 65 wherein said.micro-instruction decoding means is further responsive to other selected bits of said currently accessed micro-instruction for determining whether the selection of the microaddress of the next successive micro-instruction is dependent upon a specified condition or is independent of any conditions.

Claim 77

A data processing system in accordance with claim 69 and further including means for testing a plurality of conditions to provide a plurality of corresponding test flag bits, the state of said flag bits indicating whether one or more conditions tested are present; and means responsive to said test . flag bits for providing a condition output signal which signifies that the selection of the microaddress of the next successive micro-instruction is dependent upon a condition when one or more of said flag bits is in a state which indicates that one or more of said conditions is present or is not dependent on a condition when one of said test flag bits is in said latter state.

Claim 78

A data processing system in accordance with claim 70 wherein said condition output signal providing means includes multiplexer means responsive to said plurality of test flag bits and responsive to a selected number of bits from said current micro-instruction for selectively providing a test condition bit corresponding to one of said plurality of test flag bits; and condition logic means responsive to said selected test condition but for providing said condition output signal.

Claim 79

A data processing system having a central processor, a memory means, an arithmetic logic unit having first and second inputs capable of performing arithmetic or logical operations upon data supplied at said first and second inputs to produce an output thereform, said first and second inputs being selectively supplied to said arithmetic logic unit by multiplexer means, a register file comprising a plurality of registers capable of storing data and having said data written into and read out therefrom, a logical address bus for transferring logical addresses within said data processing system, a central processor data bus for transferring data within said data processing system, said central processor including timing means for providing a timing signal for controlling the operating time cycle of said data processing system, said central processor being responsive to macro-instructions for determining starting microaddresses of micro-instructions, a micro- sequencing means for providing one or more successive micro- instructions for use by said central processor, said microsequencing means comprising; microcontrol store means for storing a plurality of microinstructions; means for decoding said macro-instructions to produce a starting microaddress of one of said micro-instructions; said microcontrol store means being responsive to said starting microaddress for providing a micro-instruction having at least fourteen control fields stored at said microaddress of said microcontrol store means; micro-instruction decoding means responsive to said accessed micro-instruction for decoding said at least fourteen control fields, said micro-instruction decoding means comprising: means responsive to a first control field of twenty bits for generating control signals for selecting the microaddress of a next successive micro-instruction; means responsive to a second control field of four btis for generating control signals for providing output data from a selected register of said register file; which output data can be used as a first input to said arithmetic logic unit; means responsive to a third control field of four bits for generating control signals for providing output data from a selected register of said register file, which output data can be used as a second input to said arithmetic logic unit; means responsive to a fourth control field of four bits for generating control signals for controlling the supply of data from a source other than said register file during a first selected portion of said operating time cycle, which data can be used to supply an input to said arithmetic logic unit; means responsive to a fifth control field of two bits for generating control signals for controlling the supplying of data from a source other than said register file furing a second selected portion of said operating time cycle, which data can be used to supply a selected input to said arithmetic logic unit; means responsive to a sixth control field of four bits for generating control signals for controlling the shifting of selected data being operated upon by said arithmetic logic unit; means responsive to a seventh control field of three bits for generating control signals for controlling the operation of said multiplexer means to select the data to be supplied to the inputs of said arithmetic logic unit; means responsive to an eighth control field of three bits for generating control signals for controlling the logical and arithmetic operations of said arithmetic logic unit; means responsive to a ninth control field of three bits for generating control signals for controlling the destination of the output from said arithmetic logic unit; means responsive to a tenth control field of a single bit for generating control signals for controlling the type of carry operation to be used by said arithmetic logic unit; means responsive to an eleventh control field of two bits for generating control signals for controlling the source of data to be placed on said logical address bus; means responsive to a twelfth control field of five bits for generating control signals for controlling the source of data to be placed on said central processor data bus; means responsive to a thirteenth control field of three bits for generating signals for controlling the reading and writing operations of said memory means; and means responsive to a fourteenth control field of two bits for generating control signals for controlling the completion of an operation with respect to said memory means.

Claim 80

A data processing system having a central processor, a memory means, an arithmetic logic unit having first and second inputs capable of performing arithmetic or logical operations upon data supplied at said first and second inputs to produce an output thereform, said first and second inputs being selectively supplied to said arithmetic logic unit by multiplexer means, a register file comprising a plurality of registers capable of storing data and having said data written into and read out therefrom, a logical address bus for transferring logical addresses within said data processing system, a central processor data bus for transferring data within said data processing system, said central processor including timing means for providing a timing signal for controlling the operating time cycle of said data processing system, said central processor being responsive to macro-instructions for determining starting microaddresses of micro-instructions, a micro- sequencing means for providing one or more successive micro- instructions for use by said central processor, said microsequencing means comprising; microcontrol store means for storing a plurality of microinstructions; means for decoding said macro-instructions to produce a starting microaddress of one of said micro-instructions; said microcontrol store means being responsive to said starting microaddress for providing a micro-instruction having at least fourteen control fields stored at said microaddress of said microcontrol store means; micro-instruction decoding means responsive to said accessed micro-instruction for decoding said at least fourteen control fields, said micro-instruction decoding means comprising: means responsive to a first control field of twenty bits for generating control signals for selecting the microaddress of a next successive micro-instruction; means responsive to a second control field of four btis for generating control signals for providing output data from a selected register of said register file; which output data can be used as a first input to said arithmetic logic unit; means responsive to a third control field of four bits for generating control signals for providing output data from a selected register of said register file, which output data can be used as a second input to said arithmetic logic unit; means responsive to a fourth control field of four bits for generating control signals for controlling the supply of data from a source other than said register file during a first selected portion of said operating time cycle, which data can be used to supply an input to said arithmetic logic unit; means responsive to a fifth control field of two bits for generating control signals for controlling the supplying of data from a source other than said register file furing a second selected portion of said operating time cycle, which data can be used to supply a selected input to said arithmetic logic unit; means responsive to a sixth control field of four bits for generating control signals for controlling the shifting of selected data being operated upon by said arithmetic logic unit; means responsive to a seventh control field of three bits for generating control signals for controlling the operation of said multiplexer means to select the data to be supplied to the inputs of said arithmetic logic unit; means responsive to an eighth control field of three bits for generating control signals for controlling the logical and arithmetic operations of said arithmetic logic unit; means responsive to a ninth control field of three bits for generating control signals for controlling the destination of the output from said arithmetic logic unit; means responsive to a tenth control field of a single bit for generating control signals for controlling the type of carry operation to be used by said arithmetic logic unit; means responsive to an eleventh control field of two bits for generating control signals for controlling the source of data to be placed on said logical address bus; means responsive to a twelfth control field of five bits for generating control signals for controlling the source of data to be placed on said central processor data bus; means responsive to a thirteenth control field of three bits for generating signals for controlling the reading and writing operations of said memory means; and means responsive to a fourteenth control field of two bits for generating control signals for controlling the completion of an operation with respect to said memory means.

Claim 81

A data processing system in accordance with claim 72, which system further involves a plurality of scratch pad registers and an address translation means for converting logical addresses to physical addresses, said microcontrol store means providing a micro-instruction having at least two further control fields and said micro-instruction decoding means further including: means responsive to a fifteenth control field of ten bits for generating a control signal for controlling arithmetic floating point and fixed point computations by said arithmetic logic unit, for controlling operations with respect to said scratch pad

Claim 82

A data processing system in accordance with claim 72 or 73 said microcontrol store means, providing a micro-instruction having at least one other field of one bit and said micro- instruction decoding means further including: means responsive to said one other control field for detecting the odd or even parity of the micro-instruction word.

Claim 83

A data processing system in accordance with claim 74 wherein said microcontrol store providing a micro-instruction having at least five additional bits which are reserved for use in providing one or more additional control fields.

Claim 84

A data processing system in accordance with claim 75 wherein said microcontrol store means provides a micro-instruction word having a format of 80 bits, bits 0-19 defining said first control field, bits 20-23 defining said second control field, bits 24-27 defining said third control field, bits 28-31 defining said sixteenth-control field, bits 32 and 33 defining said fourth control fields, bits 34-37 defining said fifth control field, bits 38-41 defining said sixth control field, bits 42-45 defining ' said seventh control field, bits 46;48 defining said eighth control field, bits 49-51 defining said ninth control field, bit 52 defining said tenth control field, bits 53-62 defining said fifteenth control field, bits 63 and 64 defining said eleventh control field, bits 65-69 defining said twelveth control field, bits 70-72 defining said thirteenth control field, bits 73 and 74 defining said fourteenth control field, bits 75-79 being reserved for said one or more additional control fields, and bit 80 defining said seventeenth control field.

Claim 85

A data processing system capable of use with one or more external devices, said system comprising memory means including a first storage region containing a plurality of instruction routines, each routine for performing one of a plurality of selectable interrupt operations; a second storage region containing a plurality of device control tables, each said table being associate with one of said external devices and including an interrupt routine address pointing to a selected one of said interrupt routines in said first storage region; a third storage region containing a plurality of device control table addresses each of said addresses being associated with one of said external devices and pointing to a selected one of said device control tables in said second storage region; means responsive to an interrupt request from an external device for supplying an address pointing to a selected location in said third storage region when the interrupt requested by said external device is an interrupt which requires transfer of control of said data processing system to a selected one of said interrupt routines in said first storage region; and means responsive to coded information from said external device requesting said interrupt for providing an address offset from said selected location in said third storage region, the address at said offset location being the address pointing to said selected one of said device control tables in said second storage region.

Claim 86

A data processing system capable of use with one or more external devices, said system comprising memory means including a first storage region containing a plurality of instruction routines, each routine for performing one of a plurality of selectable interrupt operations; a second storage region containing a plurality of device control tables, each said table being associate with one of said external devices and including an interrupt routine address pointing to a selected one of said interrupt routines in said first storage region; a third storage region containing a plurality of device control table addresses each of said addresses being associated with one of said external devices and pointing to a selected one of said device control tables in said second storage region; means responsive to an interrupt request from an external device for supplying an address pointing to a selected location in said third storage region when the interrupt requested by said external device is an interrupt which requires transfer of control of said data processing system to a selected one of said interrupt routines in said first storage region; and means responsive to coded information from said external device requesting said interrupt for providing an address offset from said selected location in said third storage region, the address at said offset location being the address pointing to said selected one of said device control tables in said second storage region.

Claim 87

A data processing system in accordance with claim 77 wherein the device control table in said second storage region includes coded masking information for preventing other external devices from requesting interrupts when an interrupt has already been requested by said external device.

Claim 88

A data processing system having a main memory containing a plurality of segment storage regions, said system including a plurality of memory management registers each associated with one of said segment storage regions and capable of storing a 32-bit double word, said memory management registers being located externally of said main memory; accumulator storage means for storing a starting address of a block of double words stored in main memory; instruction decode means responsive to one instruction requiring the storage of said block of data words into said memory management system for providing selected control signals; means responsive to said selected control signals for accessing the first word of said block of double words at said starting address in said main memory and for loading the double words in said block into said plurality of memory management registers, said double words being loaded sequentially into said registers in a preselected order.

Claim 89

A data processing system having a main memory containing a plurality of segment storage regions, said system including a plurality of memory management registers each associated with one of said segment storage regions and capable of storing a 32-bit double word, said memory management registers being located externally of said main memory; accumulator storage means for storing a starting address of a block of double words stored in main memory; instruction decode means responsive to one instruction requiring the storage of said block of data words into said memory management system for providing selected control signals; means responsive to said selected control signals for accessing the first word of said block of double words at said starting address in said main memory and for loading the double words in said block into said plurality of memory management registers, said double words being loaded sequentially into said registers in a preselected order.

Claim 90

A data processing system having a main memory containing a plurality of segment storage regions, said system including an instruction processor unit comprising a program counter register, said program counter register containing a 32-bit double word representing the current program count in a sequence of operation being performed by said data processing system; instruction decode means responsive to an instruction occurring in said sequence of operation for requiring a program counter relative primary operation providing a plurality of decoded bits, a selected number of which formed a displacement value; and means for adding said displacement bits to the current double word in said program counter register and for placing the result into said program counter register, said result providing a reference to a specified location in the currently used segment storage region of said main memory displaced relative to the location specified by the current program count.

Claim 91

A data processing system having a main memory containing a plurality of segment storage regions, said system including an instruction processor unit comprising a program counter register, said program counter register containing a 32-bit double word representing the current program count in a sequence of operation being performed by said data processing system; instruction decode means responsive to an instruction occurring in said sequence of operation for requiring a program counter relative primary operation providing a plurality of decoded bits, a selected number of which formed a displacement value; and means for adding said displacement bits to the current double word in said program counter register and for placing the result into said program counter register, said result providing a reference to a specified location in the currently used segment storage region of said main memory displaced relative to the location specified by the current program count.

Claim 92

A data processing system for handling first data words having a first selected number of bits and second data words having a second selected number of bits less than said first number of bits; a plurality of accumulator storage means capable of storing said first or said second data words; means responsive to a second data word in a source accumulator storage means of said plurality of accumulator storage means for extending the number of bits thereof so that the number of bits of said extended data words is equal to said first selected number of bits, said extended data words being capable of storage in a destination accumulator storage means of said plurality of accumulator storage means; instruction decode means responsive to an instruction requiring the extending of said second data words for providing first selected bits of an instruction word for identifying said source accumulator storage means and second selected bits of an instruction word for for identifying said destination accumulator storage means and for providing control signals; and means responsive to said control signals for extending said second data word and for storing said extended second data word in said destination or accumulator storage means.

Claim 93

A data processing system for handling first data words having a first selected number of bits and second data words having a second selected number of bits less than said first number of bits; a plurality of accumulator storage means capable of storing said first or said second data words; means responsive to a second data word in a source accumulator storage means of said plurality of accumulator storage means for extending the number of bits thereof so that the number of bits of said extended data words is equal to said first selected number of bits, said extended data words being capable of storage in a destination accumulator storage means of said plurality of accumulator storage means; instruction decode means responsive to an instruction requiring the extending of said second data words for providing first selected bits of an instruction word for identifying said source accumulator storage means and second selected bits of an instruction word for for identifying said destination accumulator storage means and for providing control signals; and means responsive to said control signals for extending said second data word and for storing said extended second data word in said destination or accumulator storage means.

Claim 94

A data processing system in accordance with claim 81 wherein said extending means includes means for zero-extending said second data words.

Claim 95

A data processing system in accordance with claim 82 wherein said extending means.includes means for sign-extending said second data words.

Claim 96

A data processing system comprising a first destination accumulator storage means capable of storing a first selected number of bits of which only a first word having a second selected number of bits is required for an arithmetic operation; a second source accumulator storage means capable of storing a first selected number of bits of which only a second word having a second selected number of bits is required for said arithmetic operation; instruction decode means responsive to an instruction requiring multiplication of said first and second words for providing control signals for multiplying the second selected number of bits of said destination accumulator storage means and the second selected number of bits of said source accumulator storage means to produce a result having said second selected number of bits, for sign-extending said result to form a double word having said first selected number of bits, and storing said sign extended double word in said destination accumulator storage means without changing the contents of said source accumulator storage means.

Claim 97

A data processing system comprising a first destination accumulator storage means capable of storing a first selected number of bits of which only a first word having a second selected number of bits is required for an arithmetic operation; a second source accumulator storage means capable of storing a first selected number of bits of which only a second word having a second selected number of bits is required for said arithmetic operation; instruction decode means responsive to an instruction requiring multiplication of said first and second words for providing control signals for multiplying the second selected number of bits of said destination accumulator storage means and the second selected number of bits of said source accumulator storage means to produce a result having said second selected number of bits, for sign-extending said result to form a double word having said first selected number of bits, and storing said sign extended double word in said destination accumulator storage means without changing the contents of said source accumulator storage means.