Semiconductor memory device

Claim 2

A semiconductor memory device,comprising a plurality of memory blocks (MB) each of which includes a sense amplifier array (SAG) comprising a plurality of sense amplifiers (SA) and a pair of memory cell groups (CG) each comprising a plurality of dynamic-type memory cells which are selectively connected to the sense amplifier array through digit lines (DG); a row decoder (RD) for selecting a row line (RL) in the plurality of memory blocks; pairs of bus lines (BUS), each pair corresponding to one of the sense amplifier arrays; and a column decoder (CD) which is common to the plurality of memory blocks and which selectively connects a pair of input/ output terminals of the sense amplifier in each of the memory blocks to a corresponding one of the pairs of bus lines by changing the potential of each column line. (CL) connected between the column decoder and the plurality of memory blocks.

Claim 3

A device as claimed in Claim 1, wherein the column decoder (CD) is disposed along an outside edge of the area of the memory blocks (MB).

Claim 4

A device as claimed in Claim 1, wherein the column decoder (CD) is disposed between the memory blocks (MB).

Claim 5

A device as claimed in Claim 3, wherein the column decoder (CD) is disposed at the centre of the memory blocks (MB).

Claim 6

A device as claimed in Claim 1, wherein the column lines (CL) from the column decoder (CD) pass through the area of the memory blocks (MB).

Claim 7

A device as claimed in Claim 5, wherein the column lines (CL) are connected to gate transistors (Q 5 ,Q 6 ) which selectively connect the pair of input/output terminals of the sense amplifier in each of the memory blocks (MB) to a corresponding one of the pairs of bus lines (BUS).

Claim 8

A device as claimed in Claim 1, wherein each of the pairs of bus lines (BUS) is disposed parallel to the sense amplifier array (SAG) of a corresponding one of the memory blocks (MB).

Claim 10

A semiconductor memory device comprising a plurality of memory blocks (MB) each of which includes a sense amplifier array (SAG) comprising a plurality of sense amplifiers (SA) and a pair of memory cell groups (CG) each comprising a plurality of dynamic type memory cells which are connected to the sense amplifier array through digit lines (DG) and each of which comprises a capacitor and an MOS transistor, one of the electrodes of the capacitor being formed as a first conductive layer (P 1 ) and the gate electrode of the MOS transistor being formed as a second conductive layer (P 2 ); a row decoder (RD) for selecting a row line (RL) in the plurality of memory blocks; pairs of bus lines (BUS), each pair corresponding to one of the sense amplifier arrays;and a column decoder (CD) which is common to the plurality of memory blocks and which selectively connects a pair of input/output terminals of the sense amplifier in each of the memory blocks to a corresponding one of the pairs of bus lines by changing the potential of each column line (CL) connected between the column decoder and the plurality of memory blocks, the digit lines (DG) being formed as a third conductive layer having a high electrical conductivity disposed on the first conductive layer with an insulation layer (1 1 ) formed therebetween, the column lines being formed also as the third conductive layer, and the row lines (RL) being formed as a fourth layer having a high electrical conductivity disposed on the third conductive layer with another insulation layer (I 2 ) formed therebetween.

Claim 11

A semiconductor memory device comprising a plurality of memory blocks (MB) each of which includes a sense amplifier array (SAG) comprising a plurality of sense amplifiers (SA) and a pair of memory cell groups (CG) each comprising a plurality of dynamic type memory cells which are connected to the sense amplifier array through digit lines (DG) and each of which comprises a capacitor and an MOS transistor, one of the electrodes of the capacitor being formed as a first conductive layer (P 1 ) and the gate electrode of the MOS transistor being formed as a second conductive layer (P 2 ); a row decoder (RD) for selecting a row line (RL) in the plurality of memory blocks; pairs of bus lines (BUS), each pair corresponding to one of the sense amplifier arrays;and a column decoder (CD) which is common to the plurality of memory blocks and which selectively connects a pair of input/output terminals of the sense amplifier in each of the memory blocks to a corresponding one of the pairs of bus lines by changing the potential of each column line (CL) connected between the column decoder and the plurality of memory blocks, the digit lines (DG) being formed as a third conductive layer having a high electrical conductivity disposed on the first conductive layer with an insulation layer (1 1 ) formed therebetween, the column lines being formed also as the third conductive layer, and the row lines (RL) being formed as a fourth layer having a high electrical conductivity disposed on the third conductive layer with another insulation layer (I 2 ) formed therebetween.

Claim 12

A device as claimed in Claim 9, wherein the column decoder (CD) is disposed along an outside edge of the area of the memory blocks (MB).

Claim 13

A device as claimed in Claim 9, wherein the column decoder (CD) is disposed between the memory blocks (MB).

Claim 14

A device as claimed in Claim 11, wherein the column decoder (CD) is disposed at the centre of the memory blocks (MB).

Claim 15

A device as claimed in Claim 9, wherein the column lines (CL) from the column decoder (CD) pass through the area of the memory blocks (MB).

Claim 16

A device as claimed in Claim 9, wherein the first conductive layer (P 1 ) is formed continuously on a semiconductor substrate (SUB) and constitutes a common electrode of the capacitors of all memory cells of the plurality of memory blocks (MB).