A polysilicon-base self-aligned bipolar transistor process

Claim 1

Process for fabricating a bipolar transistor in a silicon substrate (10) of a first conductivity type, said substrate (10) having a planar surface, a subcollector region (11) of a second conductivity type formed in said substrate, an epitaxial layer (12) of said second conductivity type formed on said planar surface of said substrate, first and second spaced apart recessed oxide isolation regions (19A, 19B) extending through said epitaxial layer and said subcollector region into said substrate (and a third spaced apart recessed oxide isolation region (15) extending through said epitaxial layer into said subcollector region), said process including the following steps in the order recited: a) utilizing photolithography on the exposed surface of said substrate to provide a first mask (23, Figure 11) having a window (24) extending from said second recessed oxide isolation region (19B) to said third recessed oxide isolation region (15); b) ion implanting ions of said second conductivity type into the portion of said epitaxial layer exposed by the window (24) in the first mask (23) to provide a collector reach-through region (25, Figure 11); c) removing the first mask (23); d) chemically vapor depositing a layer (26, Figure 12) of polycrystalline silicon on the exposed surface of said substrate, said poly- silicon layer being doped with impurities of said first conductivity type said polysilicon layer (26) having a thickness of approximately 300 nm and an impurity concentration in the order of 10 20 atoms per cubic centimeter; e) chemically vapor depositing a first silicon dioxide layer (27) having a thickness of approximately 300 nm; f) utilizing photolithography on the exposed surface of the first silicon dioxide layer (27) to provide a mask (28, Figure 12) having first and second windows (29), said first window exposing a portion of said silicon dioxide layer (27) spaced between said first (19A) and third (15) spaced apart recessed oxide regions, said second window exposing a portion of said second silicon dioxide layer (27) over said collector reach-through region (25); g) utilizing reactive ion etch techniques to remove portions of said first silicon dioxide layer (27) and the underlying portions of said polysilicon layer (26) exposed by said windows (29) of the second mask (28, Figure 13); h) thermally growing a thin screen oxide (31, Figure 14) on the exposed surface of the substrate within said first and second windows of the second mask said thin screen oxide (31) having a thickness of approximately 30 nm; i) ion implanting said exposed surface of the substrate within said first and second windows of the second mask (28) with ions of said first conductivity type to form an intrinsic base region (32, Figure 14); j) chemically vapor depositing a second oxide layer (33, Figure 15) on the exposed surface of the substrate and on the surface of the first silicon dioxide layer (27), said second oxide layer (33) having a thickness of approximately 300 nm; k) utilizing reactive ion etching to remove said second oxide layer (33) except for the sidewall portions of this layer (33, Figure 16), these sidewall portions defining an emitter opening; I) ion implanting said exposed surface of the substrate with ions of said second conductivity type to provide an emitter region (36, Figure 17) within the intrinsic base region and to reduce the contact resistance of the reach-through region (35); m) performing a thermal cycle to anneal and activate the implemented collector reach-through region (35), the active base region (32) and the emitter region (36), also simultaneously the first conductivity type poly- silicon (26, Figure 17) will outdiffuse impurities to form the extrinsic base region (37).