EP0036093A2
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EP
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An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device
Assignee: Toshiba Corp
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Filing: 1981-02-19
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Granted: —
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Expires: 2001-02-19
Abstract
Abstract In an arithmetic control unit according to the invention, which is a one-chip high density semiconductor integrated element capable of controlling the prefetching of user's instructions with respect to a main memory, an arithmetic logic unit (ALU) (220) effects the subtraction of the content of a location counter (208) holding the location of an user's instruction to be executed next from the content of a memory address register (206) holding main memory address data, and the result of the subtraction is discriminated through gates (308, 309) connected to the ALU for determing whether or not to make prefetched instruction buffer content ineffective. An address matching mechanism (300) provided outside the chip of the arithmetic control unit according to the invention includes a comparator (303) for comparing an execution stop address set by an address switch (301) and the memory addresses. The output data of the comparator (303) is stored in a particular memory section (203x) which is provided to correspond to the prefetched instruction buffer (203), and when a microinstruction stored in the prefetched instruction buffer (203) is transferred to an instruction register (202), the data stored in the particular memory section (203x) is also read out to check for the execution stop address. Further, when making access to the main memory a particular signal indicating whether the access is pertinent is externally coupled and stored in the particular memory section (203y), so that it may be read out when reading out an instruction from the prefetched instruction buffer (203) and an illegal address interruption may be produced when it indicates that the access is inadequate.
Inventors
- 👤 Tsuneo Kinoshita
- 👤 Fumitaka Sato
- 👤 Isamu Yamazaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 09:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3812; G06F9/3804
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
209 words
An information-processing system consisting of an arithmetic control unit formed into a one-chip type by application of a highly-integrated semiconductor device, comprising: a flip-flop (309) for instructing that user instructions should be prefetched from an external main memory; means for prefetching the user instructions from the main memory while the flip-flop is set; a plurality of instruction buffers (203) for storing the user instructions prefetched from the main memory, each of said buffers having M stages each having a memory capacity of N bytes; a location counter (208) for storing a data representing the location of a user instruction to be executed next; a memory address register (206) for storing data designating the addresses of the main memory; subtracting means for subtracting the contents of the location counter from the contents of the memory address register; means for setting the flip-flop when branch is established while the user instructions are being exe- cuted or when the result R of the subtraction carried out by the subtracting means is equal to or greater than 0 and smaller than M x N (i.e. 0 < R < M x N); and means for causing the user instruction-fetching means to replace the contents of the instruction buffers while the flip-flop is set.
Claim 2
Dependent Claim
209 words
An information-processing system consisting of an arithmetic control unit formed into a one-chip type by application of a highly-integrated semiconductor device, comprising: a flip-flop (309) for instructing that user instructions should be prefetched from an external main memory; means for prefetching the user instructions from the main memory while the flip-flop is set; a plurality of instruction buffers (203) for storing the user instructions prefetched from the main memory, each of said buffers having M stages each having a memory capacity of N bytes; a location counter (208) for storing a data representing the location of a user instruction to be executed next; a memory address register (206) for storing data designating the addresses of the main memory; subtracting means for subtracting the contents of the location counter from the contents of the memory address register; means for setting the flip-flop when branch is established while the user instructions are being exe- cuted or when the result R of the subtraction carried out by the subtracting means is equal to or greater than 0 and smaller than M x N (i.e. 0 < R < M x N); and means for causing the user instruction-fetching means to replace the contents of the instruction buffers while the flip-flop is set.
Claim 3
Dependent Claim
16 words
An information-processing system according to claim 1, wherein said subtracting means is an arithmetic-logic unit (220).
Claim 4
Dependent Claim
50 words
An information-processing system according to claim 2, further comprising means for setting the flip-flop when all the bits of the output of said arithmetic-logic unit but the lowest m bits are logical "0", where m is an integral number which satisfies a formula: M x N < 2 m .
Claim 5
Dependent Claim
20 words
An information-processing system according to claim 3, wherein said means for setting the flip-flop is a logic gate circuit (308).
Claim 6
Dependent Claim
195 words
An information processing system consisting of an arithmetic control unit formed into a one-chip type by application of a highly-integrated semiconductor device, comprising: a memory address register (206) storing the logic addresses of an external main memory; a segment register (207) storing segment addresses for expanding the logic address space; a memory control, register (226) storing memory control data; a common bus (103) for supplying the logic addresses, segment addresses and memory control data to the main memory at the same time when the memory address register, segment register and memory control register are given an access to the main memory; a first external latch circuit (107) for latching the logic addresses and segment addresses supplied through the common bus; a second external latch circuit (109) for latching the memory control data supplied through the common bus; an external address conversion table for supplying physical addresses designated by the addresses supplied from the first external latch circuit; and memory-accessing means for providing an access to the main memory according to the physical addresses supplied from the external address conversion table (105 T ) and the memory control data supplied from the second external latch ciruit.
Claim 7
Dependent Claim
195 words
An information processing system consisting of an arithmetic control unit formed into a one-chip type by application of a highly-integrated semiconductor device, comprising: a memory address register (206) storing the logic addresses of an external main memory; a segment register (207) storing segment addresses for expanding the logic address space; a memory control, register (226) storing memory control data; a common bus (103) for supplying the logic addresses, segment addresses and memory control data to the main memory at the same time when the memory address register, segment register and memory control register are given an access to the main memory; a first external latch circuit (107) for latching the logic addresses and segment addresses supplied through the common bus; a second external latch circuit (109) for latching the memory control data supplied through the common bus; an external address conversion table for supplying physical addresses designated by the addresses supplied from the first external latch circuit; and memory-accessing means for providing an access to the main memory according to the physical addresses supplied from the external address conversion table (105 T ) and the memory control data supplied from the second external latch ciruit.
Claim 8
Dependent Claim
145 words
An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device, comprising: a plurality of buffers (203) for storing user instructions from an external main memory; means (105 i ) for generating a specific signal when the system is accessed to the main memory and the user instructions are thus prefetched into the buffers, said specific signal indicating whether the access of the system to the main memory is legal; a plurality of memories (203x) associated with the respective buffers for storing the specified signals; means for reading from the memories the specified signals corresponding to the user instructions when the user instructions are read from the buffers; and mans for interrupting the access of the system to the main memory when .the specified signal read from any one of the memories indicates an illegal access.
Claim 9
Dependent Claim
145 words
An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device, comprising: a plurality of buffers (203) for storing user instructions from an external main memory; means (105 i ) for generating a specific signal when the system is accessed to the main memory and the user instructions are thus prefetched into the buffers, said specific signal indicating whether the access of the system to the main memory is legal; a plurality of memories (203x) associated with the respective buffers for storing the specified signals; means for reading from the memories the specified signals corresponding to the user instructions when the user instructions are read from the buffers; and mans for interrupting the access of the system to the main memory when .the specified signal read from any one of the memories indicates an illegal access.
Claim 10
Dependent Claim
22 words
An information-processing system according to claim 6, wherein said specific signals are produced by an external address conversion table (105 T ).
Claim 11
Dependent Claim
160 words
An information processing system consisting of an arithmetic control unit into a one-chip type by. application of a highly-integrated semiconductor device, comprising: a plurality of buffers (203) for storing uer instructions from and external main memory; a plurality of memories (203x) associated with the respective buffers for storing specific data; a switch (301) provided outside the chip for designating an address to achieve address matching; a comparator (303) for comparing an address data produced by operating the switch with an memory address data which gives the system an access to the main memory; means for writing into the memories the output data of the comparator which correspond to the reading addresses of the user instructions, when the user instructions are prefetched into the buffers; and means for reading from the momories the specific data corresponding to the user instructions, thereby judging the presence or absence of an address stop, in preparation for reading of the user instructions from the buffers.
Claim 12
Dependent Claim
160 words
An information processing system consisting of an arithmetic control unit into a one-chip type by. application of a highly-integrated semiconductor device, comprising: a plurality of buffers (203) for storing uer instructions from and external main memory; a plurality of memories (203x) associated with the respective buffers for storing specific data; a switch (301) provided outside the chip for designating an address to achieve address matching; a comparator (303) for comparing an address data produced by operating the switch with an memory address data which gives the system an access to the main memory; means for writing into the memories the output data of the comparator which correspond to the reading addresses of the user instructions, when the user instructions are prefetched into the buffers; and means for reading from the momories the specific data corresponding to the user instructions, thereby judging the presence or absence of an address stop, in preparation for reading of the user instructions from the buffers.
References Cited (Backward Citations)
No citation records indexed.
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