EP0036085A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Address control means in a data processing system
Assignee: International Business Machines Corp
•
Filing: 1981-02-16
•
Granted: —
•
Expires: 2001-02-16
Abstract
Abstract The specification discloses an address control means in a data processing system which associates access registers (AR's 46) with the general purpose registers (GPR's 17) in a data processor. The AR's are each loaded with a unique STD (segment table descriptor). The STD comprises a segment table address in main storage and a segment table length field. There are 15 AR's associated respectively with 15 GPR's in a processor to define a subset of up to 15 data address spaces. The STD in an AR is selected for address translation when the associated GPR is selected as a storage operand base register, such as being the GPR selected by the B-field in an IBM System/370 instruction. The arrangement allows each AR to specify that it does not use the STD in its associated AR to define its data address space, but instead uses the STD in the program address space AR. However, the STD content of an AR is not selected for an address translation if the associated GPR is selected for a purpose other than as a storage operand base register, such as if a GPR is selected as an index (X) register or as a data source or sink register (R) for an instruction. A sixteenth AR may be provided to define and control the executing program address space, which may also contain data. The arrangement obtains authority and other control for access to and use of the content in each address space by also associating an AR Control Vector (ARCV) register with each AR.
Inventors
- 👤 Justin Ralph Butwell
- 👤 Casper Anthony Scalzi
- 👤 Richard John Schmalz
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 17:41
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458; G06F12/1466; G06F12/1475; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
127 words
Address control means in a data processing system having a predetermined number of general purpose registers (GPR's 17) in which some instructions of the system specify a GPR as a storage operand base register which content takes part in a calculation of the instructions logical storage operand address, characterised by: a plurality of access registers (AR's 46) respectively associated with the GPR's, means (40 to 42) for accessing the content of the AR associated with a GPR being accessed, the AR content having an address space identifier (ASI), and address translation means (18 to 33) receiving a requested storage operand address and the ASI from the accessing means for translating the storage operand address to a real address in a main storage of the data processing system.
Claim 2
Dependent Claim
127 words
Address control means in a data processing system having a predetermined number of general purpose registers (GPR's 17) in which some instructions of the system specify a GPR as a storage operand base register which content takes part in a calculation of the instructions logical storage operand address, characterised by: a plurality of access registers (AR's 46) respectively associated with the GPR's, means (40 to 42) for accessing the content of the AR associated with a GPR being accessed, the AR content having an address space identifier (ASI), and address translation means (18 to 33) receiving a requested storage operand address and the ASI from the accessing means for translating the storage operand address to a real address in a main storage of the data processing system.
Claim 3
Dependent Claim
63 words
Address control means as defined in Claim 1, further comprising: instruction unit means for detecting the GPR field(s) in each instruction being decoded, including AR detecting means for detecting each GPR field addressing a GPR containing an operand address in an address space, and an AR address signal being outputted by the AR detecting means to the accessing means for selecting an AR.
Claim 4
Dependent Claim
107 words
Address control means as defined in Claim 2, in which the data processing system has a control register for containing a program ASI for defining the address space of a program being executed, further comprising: instruction fetch controls providing a logical address for each instruction fetch request, the address translation means receiving the program ASI content of the control register for translating the instruction fetch address to a real address in main storage for the program being executed from which instruction fetches occur, whereby the program is in a program address space and can access data in any address space specified by the content of an AR.
Claim 5
Dependent Claim
140 words
Address space control means as defined in Claim 1, further comprising: instruction fetch control means providing a logical address for each instruction fetch request, operand access control means providing a logical address for each operand access request, program space access control means for accessing the ASI content of an AR associated with an executing program when an instruction fetch request is provided, data space access control means for accessing the ASI content of an AR associated with a GPR selected by an operand access request, the translation controls receiving the ASI provided by either the program space access control means or the data space access control means, whereby the AR accessed by the data space access control means may specify a data address space, while the AR accessed by the program space access control means specifies the program address space.
Claim 6
Dependent Claim
50 words
Address control means as defined in Claim 1, further comprising: access register control vector (ARCV) registers being respectively associated with the plurality of AR's, each ARCV register containing control bits for regulating the operation of the data processing system when accessing a data address space specified in the associated AR.
Claim 7
Dependent Claim
44 words
Address control means as defined in Claim 1, further comprising: access register control vector (ARCV) registers being respectively associated with the plurality of AR's, the content of each ARCV register controlling the mode of access to an address space identified in the associated AR.
Claim 8
Dependent Claim
133 words
Address control means as defined in Claim 6, further comprising: each ARCV register containing an enable/disable bit position set to on/off state, the state of the enable/disable bit position being sensed by the accessing means, transfer means in the accessing means for transferring to the address translation means the content of the AR selected by a GPR designated as a storage operand register field of an instruction if the enable/disable bit position is set to an enable state, the transferring means not transferring said AR contents if the enable/disable bit position is set to a disabled state, whereby when the enable/disable bit is set to the disabled state, the address translation means interprets the operand address in the same way as in a system in which the AR's and ARCV's do not exist.
Claim 9
Dependent Claim
82 words
Address control means as defined in Claim 6, further comprising: the ARCV register associated with each operand AR containing at least a write authority protection field, the protection field being accessed by the accessing means, means for signalling storage write request signals from an instruction execution unit, program interrupt means being actuated by the write request signal when the write authority protection field is off, whereby the operand address translation is interrupted if the request does not have the required access authority.
Claim 10
Dependent Claim
83 words
Address control means as defined in Claim 6, further comprising: the ARCV register associated with each operand AR containing at least a read authority protection field, the protection field being accessed by the accessing means, . means for signalling storage read request signals from an instruction execution unit, program interrupt means being actuated by the read request signal when the read authority protection field is off, whereby the operand address translation is interrupted if the request does not have the required access authority.
Claim 11
Dependent Claim
68 words
Address control means as defined in Claims 8 or 9, further comprising: a program ARCV register associated with a program AR, the program ARCV register containing an access authority protection field, the program interrupt means being actuated by an operand access request signal to the program address space if the request does not have the authority indicated by the access authority protection field in the program ARCV register.
Claim 12
Dependent Claim
100 words
Address control means as defined in Claim 1, further comprising: a control register for containing address information for locating ASI data in main storage which are to be loaded into the AR's, instruction unit means for interpreting a load AR instruction specifying an AR to be loaded and a main .storage address of the ASI data to be loaded into the AR, main storage means for accessing the ASI data at the storage address into a storage out register, and means to load the ASI data into the designated AR to identify an address space to the data processing system.
Claim 13
Dependent Claim
71 words
Address control means as defined in Claim 11, further comprising: access register control vector (ARCV) registers being respectively associated with the plurality of AR's, each ARCV register containing control bits for regulating the operation of the data processing system when accessing a data address space specified in the associated AR, the loading means also loading a subset of the ASI data into an ARCV register associated with the AR being loaded.
Claim 14
Dependent Claim
48 words
Address control means as defined in Claim 11, further comprising: means to test an enable field in the storage out register to determine if the ASI data is valid, and means to inhibit loading the ASI data into the specified AR if the ASI data is not valid.
Claim 15
Dependent Claim
80 words
Address control means as defined in Claim 1, further comprising: a control register for containing address information for locating an area in main storage into which the content of an AR can be stored, instruction unit means for interpreting a store AR instruction specifying an AR having contents to be stored at an address in main storage determined from the address information in the control register, and main storage means for storing the AR contents into the main storage address.
Claim 16
Dependent Claim
39 words
Address control means as defined in Claim 14, further comprising: an ARCV register associated with the AR specified in the store AR instruction, the content of the ARCV register being stored in main storage along with the AR content.
Claim 17
Dependent Claim
54 words
Address control means as defined in Claim 5, further comprising: instruction unit means for interpreting a disable/enable AR instruction, an enable/disable bit associated with a specified AR, means responsive to the instruction unit means for setting the enable/disable bit for the particular AR to an on or off state as indicated in the instruction.
Claim 18
Dependent Claim
47 words
Address control means as defined in Claim 5, further comprising: one of the AR and its corresponding ARCV register (called an AR/ARCV pair) being predesignated to control a program address space for an executable program, and the remaining AR/ARCV pairs being available to control data address spaces.
Claim 19
Dependent Claim
49 words
Address control means as defined in Claim 17, further comprising: an enable/disable field in each ARCV register, any of the remaining AR/ ARCV pairs having its enabled/disabled field set to a disabled state having its corresponding GPR associated with the program address space defined in the one AR/ARCV pair.
Claim 20
Dependent Claim
58 words
Address control means as defined in Claim 18, further comprising: the ARCV register in the one AR/ARCV pair having a plurality of privileged instruction subclass mask bits respectively associated with different subclasses of privileged instructions, program interrupt means actuated by operational decoding of an instruction in a subclass having its mask bit disabled in the one AR/ARCV pair.
Claim 21
Dependent Claim
47 words
Address control means as defined in Claim 17, further comprising: each ARCV register having authority control bits to control read or write accesses in the corresponding address space, program interrupt means actuated by any disabled authority bit when an access request attempts to violate the disabled authority.
Claim 22
Dependent Claim
44 words
Address control means as defined in Claim 1, further comprising: the address translation means using each ASI as a segment table descriptor (STD) to locate a particular segment table, whereby each requested logical address is accessed into the address space defined by a STD.
Claim 23
Dependent Claim
23 words
Address control means as defined in Claim 17;further comprising: an array in which each addressed location contains the registers for an AR/ARCV pair.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.