Modular system controller for a transition machine

Claim 2

A general purpose computing machine operable for transitioning between states for solving an algorithm and comprising: a) a plurality of data processors (2a...2c) each including computing means for computing data in accordance with application programs; b) data memory storage means -(4) having at least a portion thereof shared by said plurality of data processors (2a...2c); c) application program memory storage means (4) for storing said application programs; and d) a modular hardware system controller (10) operable for determining the eligibility of each of said application programs and for enabling operation of different ones of said data processors (2a...2c) for concurrent execution of said eligible application programs, said system controller (10) enabling--expansion of machine throughput by addition of modular components (225; 325) thereto.

Claim 3

A general purpose computing machine as recited in claim 1, wherein said system controller (10) is operable for determining eligibility based on a plurality of unary predicates associated with the applicability of the transitions between states of said machine for solving said algorithm.

Claim 4

A general purpose computing machine as recited in claim 2, wherein said application programs are event-driven data transformation programs without direct transfer of control therein or to other application. programs.

Claim 5

A modular hardware executive apparatus for use in a multiprocessing system for concurrent operation of a plurality of data processors (2a...2c) for solving computational problems defined by a plurality of application programs and corresponding control programs, said data processors (2a...2c) connected for accessing said plurality of application programs stored in application program memory storage means and data stored in data memory storage means (4) including at least a common data memory area accessible by said plurality of data processors (2a...2c), said hardware executive apparatus connected to said plurality of data processors (2a...2c) and executing said control programs and comprising: a) at least one status storage means for storing binary status indications S . corresponding to data conditions on a data set appropriate for determining eligibility of said application programs solving said computational problems, whereby said stored status indications correspond to data conditions which are relevant for enabling execution of application programs by said plurality of processors (2a...2c) which are utilized in solving said computational problems; b) a plurality of modular units (225), each unit including a relevance storage means for storing groups, i, of relevance indications R.. each group corresponding to the relevance of at least some of said status indications to the i th one of said application programs where i is an integer designating one of said groups and corresponding one of said application programs and j is an integer designating one of said status indications; c) means (220) .connected to said at least one status storage means and responsive to said data processors (2a...2c) for updating said status indications stored in said status storage means at the completion of execution of said i th application program, said updating means including means for modifying a plurality of said status indications in response to completion of execution of one of said application.programs; d) means (218) connected to at least one of said relevance storage means and said at least one status storage means for determining the eligibility of at least some of said application programs for execution by said plurality of processors (2a...2c); and e) means (214) responsive to said eligibility determining means (21.8) and operatively connectable to said data processors (2a...2c) for enabling execution of eligible application programs by said plurality of data processors whereby at least some of said application programs which are determined eligible may be executed concurrently.

Claim 6

A modular hardware executive apparatus for use in a multiprocessing system for concurrent operation of a plurality of data processors (2a...2c) for solving computational problems defined by a plurality of application programs and corresponding control programs, said data processors (2a...2c) connected for accessing said plurality of application programs stored in application program memory storage means and data stored in data memory storage means (4) including at least a common data memory area accessible by said plurality of data processors (2a...2c), said hardware executive apparatus connected to said plurality of data processors (2a...2c) and executing said control programs and comprising: a) at least one status storage means for storing binary status indications S . corresponding to data conditions on a data set appropriate for determining eligibility of said application programs solving said computational problems, whereby said stored status indications correspond to data conditions which are relevant for enabling execution of application programs by said plurality of processors (2a...2c) which are utilized in solving said computational problems; b) a plurality of modular units (225), each unit including a relevance storage means for storing groups, i, of relevance indications R.. each group corresponding to the relevance of at least some of said status indications to the i th one of said application programs where i is an integer designating one of said groups and corresponding one of said application programs and j is an integer designating one of said status indications; c) means (220) .connected to said at least one status storage means and responsive to said data processors (2a...2c) for updating said status indications stored in said status storage means at the completion of execution of said i th application program, said updating means including means for modifying a plurality of said status indications in response to completion of execution of one of said application.programs; d) means (218) connected to at least one of said relevance storage means and said at least one status storage means for determining the eligibility of at least some of said application programs for execution by said plurality of processors (2a...2c); and e) means (214) responsive to said eligibility determining means (21.8) and operatively connectable to said data processors (2a...2c) for enabling execution of eligible application programs by said plurality of data processors whereby at least some of said application programs which are determined eligible may be executed concurrently.

Claim 7

A hardware executive apparatus as recited in claim 4, wherein said data processors solve a plurality of disjoint computational problems, said disjoint computational problems defined by different groups of application programs, and wherein said relevance storage means of each modular unit stores relevance indications associated with a different group of application programs.

Claim 8

A hardware executive apparatus as recited in claim 5, wherein said at least one status storage means comprises a plurality of separate status storage means, said updating means comprises a plurality of separate updating means, said eligibility determining means comprises a plurality of separate eligibility determining means and said execution enabling means comprises a plurality of separate execution enabling means, each modular unit further including one of said plurality of separate status storage means, one of said plurality of separate updating means, one of said plurality of separate eligibility determining means and one of said plurality of separate execution enabling means, wherein each modular unit forms a separate hardware executive apparatus for a different group of application programs.

Claim 9

A hardware executive apparatus as recited in claim 6, wherein each of said separate status storage means comprises a status register having bit storage positions corresponding to binary status indications on a different, disjoint data set corresponding to said different groups of application programs.

Claim 10

A hardware executive apparatus as recited in claim 7, wherein each bit storage position of each of said status storage registers corresponds to one status indication.

Claim 11

A hardware executive apparatus as recited in claim 8, wherein each of said relevance storage means comprises a relevance matrix storage means wherein each of said groups, i, form rows (columns) of said matrix storage means and individual binary relevance indications form columns (rows) of said matrix, each column (row) corresponding to one of said status indications on said data set.

Claim 12

A hardware executive apparatus as recited in claim 9, wherein for any given modular unit, said separate means for determining the eligibility of ' application program i comprises means for forming a logical operation with each status indication S. stored in said status storage register of said given modular unit and each corresponding relevance indication R .. stored in said relevance matrix storage means of said given modular unit, such that, in said given modular unit, application program i is eligible if all status indications S . in said given modular unit corresponding to relevance indications R .. are true.

Claim 13

A hardware executive apparatus as recited in claim 10, wherein, in said given modular unit, said means for updating said status indications comprises: a) means for sensing the completion of execution of each application program i of said given modular unit; b) means for storing fixed status indications (T,F) associated with each application program i, of said given modular unit, said fixed status indications determined by a given one of said computational problems independently of values of said associated data set; c) means for storing variable status indications (V) associated with completion of application program i of said given modular unit, said variable status indications determined by said given computational problem in dependence upon calculations of said data processors on said associated data set; and d) logic circuit means for combining said stored fixed status indications and said variable status indications for generating update status indications for storage in said status storage means of said given modular unit.

Claim 14

A modular computing system comprising: a) a plurality of data processors accessing application programs stored in application program memory storage means and data stored in data memory storage means, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors; b) a plurality of Z modular units, each modular unit including: 1) a status register for storing M binary status indications of M data conditions appropriate for partially determining the eligibility of said application programs stored in said application program memory storage means, Z and M being integers; 2) - a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of said application programs; and 3) means for updating said M binary status indications of said status register in response to changes of the binary status of said data conditions upon execution of said application programs; c) means for storing a plurality of application program designation addresses corresponding to said application programs; d) means for determining the eligibility of said application programs for execution by said plurality of data processors, said eligibility determining means responsive to said ZM binary status indications of said Z status registers and said corresponding ZM binary relevance indications of said Z relevance matrix stores; e) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible; and f) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby Z modular units may be utilized in said computing system for increasing the number of data conditions for a computational problem to be solved by said computing system.

Claim 15

A modular computing system comprising: a) a plurality of data processors accessing application programs stored in application program memory storage means and data stored in data memory storage means, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors; b) a plurality of Z modular units, each modular unit including: 1) a status register for storing M binary status indications of M data conditions appropriate for partially determining the eligibility of said application programs stored in said application program memory storage means, Z and M being integers; 2) - a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of said application programs; and 3) means for updating said M binary status indications of said status register in response to changes of the binary status of said data conditions upon execution of said application programs; c) means for storing a plurality of application program designation addresses corresponding to said application programs; d) means for determining the eligibility of said application programs for execution by said plurality of data processors, said eligibility determining means responsive to said ZM binary status indications of said Z status registers and said corresponding ZM binary relevance indications of said Z relevance matrix stores; e) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible; and f) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby Z modular units may be utilized in said computing system for increasing the number of data conditions for a computational problem to be solved by said computing system.

Claim 16

A modular computing system as recited in claim 12, wherein said eligibility determining means comprises: a) a procedure eligibility determination circuit for each modular unit, each of said circuits providing a component eligibility output signal in response to the associated M binary status indications and M binary relevance indications of each of said application programs; and b) means responsive to said component eligibility output signals from each modular unit for providing an eligibility determination signal whereby said eligibility determination signal is responsive to said ZM binary status indications and said ZM binary relevance indications for each of said application programs, and wherein said synchronization and control logic circuit means is operative in response to said eligibility determination signal for enabling generation of said designation addresses.

Claim 17

A modular computing system as recited in claim 13, wherein said procedure eligibility determination circuit for each modular unit comprises means for forming a logical operation with each of said associated M binary status indications and each corresponding M binary relevance indications for each of said application programs such that a logically true component eligibility output signal is provided only if all logically true (relevant) binary relevance indications correspond to logically true (data condition true) binary status indications, and said means for providing said eligibility determination signal comprises means for logically combining said component eligibility output signals such that a logically true eligibility determination signal is provided only if all of said component eligibility output signals are logically true.

Claim 18

A modular computing system as recited in claim 13 further comprising means for storing an application program type indication associated with each of said application programs stored in said application program memory storage means and wherein said eligibility determining means further comprises a comparison circuit for comparing the type of processor seeking access to said application programs with the stored application program type designation and for providing an additional component eligibility output signal, said eligibility determination signal means responsive to said additional component eligibility output signal for providing said eligibility determination signal.

Claim 19

A modular computing system as recited in claim 12 further comprising an interface means connected between said system controller and said plurality of data processors wherein said interface means comprises a binary mode indication register (X) loaded by said data processors for identifying entry and exit modes of operation; said system operable in said entry mode of operation in response to loading of said mode indication register by the k th one of said plurality of data processors for determining eligibility of the i th one of said plurality of application programs for execution by said k th data processor and for generating an application program designation address corresponding to said i th application program for storage in said interface means for loading by said k th data processor whereby said k data processor executes said i th application program; and said system operable in said exit mode in response to loading of said mode indication register by said k th data processor for receiving application program identifying data of said i th application program for enabling said updating means to update said status register, said k th data processor identifying chances of the binary status of said data conditions as a result of execution of said i th application program, wherein k is an integer designating one of said data processors and i is an integer designating one of said application programs.

Claim 20

A modular computing system as recited in claim 16, wherein each modular unit further comprises: means for storing fixed status modifying indications (T,F) for modifying said status storage register upon completion of execution of said i th application program, said fixed status modifying indications determined by said computational problem to be solved independent of data values computed in said k th data processor; and said interface means further comprises means for storing variable status modifying indications (V) associated with completion of said i th application program, said variable status modifying indications determined by said data values computed in said k th data processor, each of said updating means receiving said fixed status modifying indications and said variable status modifying indications for determining updated binary status indications of said data conditions and for storing same in each of said status registers.

Claim 21

A modular computing system comprising: a) a plurality of data processors accessing application programs stored in application program memory storage means and data stored in data memory storage means, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors; b) a system controller comprising: 1) a status register for storing M binary status indications of a plurality of M data conditions appropriate for determining the eligibility of up to ZN application programs stored in said application program memory storage means, Z, M and N being integers and N being less than the number of application programs stored in said application program memory storage means and utilized for solving a computational problem by said computing system, 2) a plurality of Z modular units, each modular unit including: i) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of as many as N application programs, said relevance indications being different from one modular unit to another and corresponding to different groups of application programs, each group having as many as N application programs; ii) means for updating said binary status indications of said status register in response to changes of the binary status of said data conditions upon execution of said application programs; and iii) means for storing up to ZN application program designation addresses corresponding to said application programs; 3) means for determining the eligibility of said up to ZN application programs for execution by said plurality of data procesfors, said eligibility determining means responsive to said M binary status indications of said status register and said M corresponding binary relevance indications of said relevance matrix store; and 4) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible; and c) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby any number of Z modular units may be utilized in said computing system for increasing the number of application programs utilized for solving a computational problem by said computing system.

Claim 22

A modular computing system comprising: a) a plurality of data processors accessing application programs stored in application program memory storage means and data stored in data memory storage means, said data memory storage means having at least a data memory area commonly accessible by said plurality of data processors; b) a system controller comprising: 1) a status register for storing M binary status indications of a plurality of M data conditions appropriate for determining the eligibility of up to ZN application programs stored in said application program memory storage means, Z, M and N being integers and N being less than the number of application programs stored in said application program memory storage means and utilized for solving a computational problem by said computing system, 2) a plurality of Z modular units, each modular unit including: i) a relevance matrix store for storing binary indications of the relevance of each of said M data conditions to each of as many as N application programs, said relevance indications being different from one modular unit to another and corresponding to different groups of application programs, each group having as many as N application programs; ii) means for updating said binary status indications of said status register in response to changes of the binary status of said data conditions upon execution of said application programs; and iii) means for storing up to ZN application program designation addresses corresponding to said application programs; 3) means for determining the eligibility of said up to ZN application programs for execution by said plurality of data procesfors, said eligibility determining means responsive to said M binary status indications of said status register and said M corresponding binary relevance indications of said relevance matrix store; and 4) logic circuit means for synchronizing and controlling said modular units, said logic circuit means operative in cooperation with said application program designation address storing means for generating designation addresses for application programs determined to be eligible; and c) interface means for interconnecting said Z modular units and said logic circuit means with said plurality of data processors, said interface means receiving said designation addresses and storing same for access by said plurality of data processors whereby a plurality of eligible programs may be executed concurrently, and whereby any number of Z modular units may be utilized in said computing system for increasing the number of application programs utilized for solving a computational problem by said computing system.

Claim 23

A modular computing system as recited in claim 18, wherein said means for determining eligibility of said up to ZN application programs comprises a procedure eligibility determination logic circuit for each modular unit, each procedure eligibility determination logic circuit providing a' component eligibility output signal and said system controller further comprising: a priority selection circuit responsive to said component eligibility output signals for enabling said synchronization and control logic circuit means to generate an application program designation address and for generating module selection signals corresponding to a selected modular unit, and multiplexing means connected between said interface means and said plurality of modular units and responsive to said module selection signals . for feeding application program designation addresses from said selected modular unit to said interface means.

Claim 24

A modular computing system as recited in claim 19, wherein said interface means comprises: a) an execute register for storing application program designation addresses, and b) an index register for storing identifying representations of modular units and application programs controlled by said modular units.

Claim 25

A modular computing system as recited in claim 20, wherein said interface means comprises a binary mode indication register (X) loaded by said data processors for identifying entry and exit modes of operation: said system operable in said entry mode of operation in response to loading of said mode indication register by the k th one of said plurality of data processors for determining eligibility of the i th one of said application programs for execution by said k th data processor and for generating an application program designation address corresponding to said i th application program for storage in said execute register of said interface means for loading by said k th data processor whereby said k th data processor executes said i application program; and said system operable in said exit mode in response to loading of said mode indication register by said k th data processor for receiving application program identifying data of said i th application program loaded by said k th data processor into said index register of said interface means for enabling said updating means to update said status register, said K th data processor identifying changes of the binary status of said data conditions as a result of execution of said i th application program, wherein k is an integer designating one of said data processors and i is an integer designating one of said application programs.

Claim 26

A modular computing system as recited in claim 21, wherein each modular unit further comprises: means for storing fixed status modifying indications (T,F) for modifying said status register upon completion of execution of said i th application program, said fixed status modifying indications determined by said computational problem to be solved independent of data values computed in said k th data processor; and . said interface means further comprises means for storing variable status modifying indications (V) associated with completion of said i th application program, said variable status modifying indications determined by said data values computed in said k th data processor, each of said updating means receiving said fixed status modifying indications and said variable status modifying indications of said data conditions and for storing same in each of said status registers.