Diagnostic circuit for PCM connection networks

Claim 1

Diagnostic circuit for a PCM connection network, able to pick up from the network and transfer to the network control device the bits relating to a PCM channel chosen out of a plurality of incoming or outgoing PCM groups, the circuit receiving from the control device, in message form, the data relative to the identities of the channel, the group and the frame involved in the test, a test start command and a reset command, and receiving also enable and control signals necessary to its operation, characterized in that it comprises: - a selector (MX) having a plurality of inputs each connected to one of said groups (Fe, Fu) and a single output on which the bits relating to the chosen channel are presented in series; - a series-to-parallel converter (SP), connected to the output of the selector (MX) to parallelize said bits; - a logic network (RL) to decode the messages and the signals sent by the control device (CN) and to control the pick up and transfer operations; - a data transceiver (BD), connected on the one hand to a data bus (10) that carries to the circuit (CT1, CT2) the messages sent by the control device and transfers to the control device the bits picked up, and connected on the other side to the series-to-parallel converter (SP) and to the logic network (RL); - a time base (BT) that is slaved to the timing of the connection network (RC) by means of two signals (t,, t Z ) corresponding to the frame timing and to half the bit time, and generates signals representing the channel time and the bit time; said logic network (RL) comprising: - a first decoder (DEI) enabling the circuit (CR1, CT2) to the operation; - a second decoder (DE2) that decodes the requests for operation and a signal indicating whether the circuit (CT1, CT2) must load a message .supplied by the control device or must transfer thereto the bits picked up; said decoder being enabled by the first decoder (DEI) and having a first output (35) that is excited in presence of the signal indicating the arrival of a message and a second output (34) connected to the transceiver (BD) and excited in presence of a bit transfer command; - a third decoder (DE3), that is enabled by the excitation of the first output (35) of the second decoder (DE2) and recognizes the kind and the contents of the message coming from the control device, on the basis of one bit of each message and of a signal (DC) also sent by the control device and indicating whether the message contains data or commands, said third decoder having two outputs (38, 39) that are excited upon the recognition of a test start message or a reset message respectively and a group of further outputs (36, 37) respectively excited upon recognition of a particular data message; - a synchronizing device (SN) that is enabled by the frame timing signal (t,) to let through a test start signal it receives through the third decoder (DE3); - presettable counting means (CR1, CR2) that load the data about the identity of the channel, the group and the frame when said further outputs (36, 37) of the third decoder (DE3) are excited and that begins to count under the control of said synchronizing circuit (SN); - a parallel-to-parallel register (PP), that receives at one input the signals identifying the group (Fe, Fu) involved in the test and presents them to the output as control signals for the positioning of said selector (MX); - a fourth decoder (DE4) that receives at the input the signals of end-of-counting from said counting means and has an output (42) connected to said series-to-parallel converter (SP) to enable the load and parallelization of the bits picked up in series by the selector (MX); - a "data ready" circuit (DP) informing the control device of the bit availability, said circuit being enabled by the fourth decoder (DE4) at the end of the loading of the bits in the converter (SP) and disabled by the excitation of the second output (34) of the second decoder (DE2).