EP0034653A1
Expired / Lapsed
EP
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Dual electron injector structures
Assignee: International Business Machines Corp
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Filing: 1980-10-23
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Granted: —
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Expires: 2000-10-23
Abstract
Abstract Dual electron injection structures having an insulator (5) with at least two graded or stepped composition regions (1,3) vertically disposed therein and wherein one (1) of said graded composition regions is situated adjacent to the gate electrode 2 to inject electrons when a negative voltage bias is applied, andat least a second graded or stepped composition is situated adjacent to a floating gate to inject electrons when a positive bias is applied, said injections occurring at low to moderate voltages. A desired I-V characteristic can be obtained for a non-volatile memory device for each voltage polarity by stacking the appropriate insulators between the contacts. Whrite and erase characteristics of non-volatile semiconductor memories employing floating polysilicon storage layers and a dual electron injection structure between the control gate and floating gate can be tailored separately, both being independent of the read operation, which is controlled by a surface channel in the substrate Si. Write and erase characteristics of non-volatile semiconductor memories employing floating polysilicon storage layers and a dual electron injection structures between the control gate and floating gate can be tailored separately, both being independent of the read operation which is controlled by a surface channel in the substrate Si.
Inventors
- 👤 Donelli Joseph Di Maria
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 05:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/682; H10N; H10N70/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
92 words
A dual electron injector structure, characterized by an insulator (5) with at least two graded or stepped composition regions (1, 3) vertically disposed therein and wherein one (1) of said graded composition regions is situated proximate to the upper surface of said structure to inject electrons when a negative voltage bias is applied, and at least a second graded or stepped composition insulator (3) is situated proximate to the opposing surface of said device to inject electrons when a positive voltage bias is applied, said injections occurring at low to moderate voltages.
Claim 2
Dependent Claim
92 words
A dual electron injector structure, characterized by an insulator (5) with at least two graded or stepped composition regions (1, 3) vertically disposed therein and wherein one (1) of said graded composition regions is situated proximate to the upper surface of said structure to inject electrons when a negative voltage bias is applied, and at least a second graded or stepped composition insulator (3) is situated proximate to the opposing surface of said device to inject electrons when a positive voltage bias is applied, said injections occurring at low to moderate voltages.
Claim 3
Dependent Claim
52 words
The structure as claimed in claim 1, characterized by a silicon substrate having thereon a silicon dioxide insulator layer (5) and an electrical contact (2) on the silicon dioxide insulator layer, said silicon dioxide insulator layer having vertically disposed therein regions (1, 3) of graded or stepped compositions near its opposing surfaces.
Claim 4
Dependent Claim
30 words
The structure as claimed in claim 2, characterized in that said graded or stepped composition regions (1, 3) are composed of silicon dioxide containing increasing or constant excess silicon content.
Claim 5
Dependent Claim
50 words
The structure as claimed in claim 1, characterized by a silicon substrate having thereon a silicon nitride insulator layer (5) and an electrical contact (2) on the silicon nitride layer, said silicon nitride layer having vertically disposed therein, regions (1, 3) of graded or stepped compositions near its opposing surfaces.
Claim 6
Dependent Claim
32 words
The structure as claimed in claim 2 or 4, characterized in that said graded or stepped composition regions (1, 3) are composed of silicon nitride containing increasing or constant excess silicon content.
Claim 7
Dependent Claim
64 words
A MGOS FET structure, characterized by at least two injection regions (1, 3) vertically disposed therein and wherein one said injection region (1) is situated adjacent to the gate electrode (2, Vg) and at least the second of which is situated adjacent to a floating gate or an electron trapping region (4), said injection regions comprising regions of graded or stepped excess Si composition.
Claim 8
Dependent Claim
64 words
A MGOS FET structure, characterized by at least two injection regions (1, 3) vertically disposed therein and wherein one said injection region (1) is situated adjacent to the gate electrode (2, Vg) and at least the second of which is situated adjacent to a floating gate or an electron trapping region (4), said injection regions comprising regions of graded or stepped excess Si composition.
Claim 9
Dependent Claim
40 words
The MGOS FET structure as claimed in claim 7, characterized in that the gate structure is composed of an oxide (5) formed on a silicon substrate and having near its opposing surfaces regions of graded or stepped excess silicon concentrations.
Claim 10
Dependent Claim
41 words
The MGOS FET structure as claimed in claim 7, characterized in that the gate structure is composed of a nitride layer (5) formed on a silicon substrate and having near its opposing surfaces regions of graded or stepped excess silicon concentrations.
Claim 11
Dependent Claim
30 words
The MGOS FET structure as claimed in claim 8, characterized in that said regions (1, 3) of graded or stepped excess silicon concentrations consist of Si rich Si0 2 .
Claim 12
Dependent Claim
32 words
The MGOS FET structure as claimed in claim 8, characterized in that said regions (1, 3) of graded or stepped excess silicon concentrations consist of Si rich Si 3 N 4 .
Claim 13
Dependent Claim
100 words
In a MOSFET device for performing a memory function, said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions, characterized in that the insulator (5) of the insulated gate structure has disposed near its opposing surfaces regions (1, 3) of graded or stepped concentrations of Si to provide at least two regions wherein electrons can be injected from either of the opposing regions, depending on voltage bias, into the insulator under low to moderate field conditions at the gate electrical contact.
Claim 14
Dependent Claim
100 words
In a MOSFET device for performing a memory function, said device being of the type comprising a silicon substrate having source and drain regions formed therein and an insulated gate structure formed between said source and drain regions, characterized in that the insulator (5) of the insulated gate structure has disposed near its opposing surfaces regions (1, 3) of graded or stepped concentrations of Si to provide at least two regions wherein electrons can be injected from either of the opposing regions, depending on voltage bias, into the insulator under low to moderate field conditions at the gate electrical contact.
Claim 15
Dependent Claim
66 words
The MOSFET device as claimed in claim 12, characterized in that the insulator (5) comprises a thermal oxide having regions (1, 3) of graded or stepped excess Si concentrations therein, one of such regions being in the vicinity of the gate electrical contact interface (2) and at least a second such region being in the vicinity of a floating gate or an electron trapping region (4).
Claim 16
Dependent Claim
65 words
The MOSFET device as claimed in claim 13, characterized in that the insulator (5) comprises a nitride layer having regions (1, 3) of graded or stepped excess Si concentrations, one of such regions being in the vicinity of the gate electrical contact interface (2) and at least a second such region being in the vicinity of a floating gate or an electron trapping region (4).
Claim 17
Dependent Claim
68 words
The MOSFET device as claimed in claim 13, characterized in that the insulator (5) comprises an oxide layer having regions (1, 3) of Si 3 N 4 with graded or stepped Si concentrations one of such regions being in the vicinity of the gate electrical contact interface (2) and at least a second such region being in the vicinity of a floating gate or charge trapping layer (4).
References Cited (Backward Citations)
US4104675A
Cited
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