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EP0032992A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Circuit for interfacing a half-duplex digital data line with a simplex transmitting and a simplex receiving line, and vice-versa

Assignee: International Business Machines Corp
•
Filing: 1980-12-04
•
Granted: —
•
Expires: 2000-12-04
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Abstract

Abstract The present circuit, which serves as a twin simplex/half- duplex interfacing, includes a triple input NAND gate (28), the output of which is connected directly to the outgoing simplex conductor (30). Signals on the incoming simplex conductor (34) are applied to the three inputs of NAND gate (28) through separate signals paths which introduce different delays. One signal path introduces an intermediate delay before applying the incoming signal to NAND gate (28) in an inverted form. The half-duplex line (16) is connected to this signal path. While incoming signals are applied at all three inputs to NAND gate (28) as well as to the half-duplex line (16), a lack of coincidence at the inputs prevents any incoming signal from passing through the circuit to the outgoing simplex line (30).

Inventors

  • 👤 James Stanley Kolodzey
  • 👤 Francis Edward Noel, Jr.
  • 👤 George Raymond Stilwell, Jr.

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-03 11:36
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/16; H04L25/00; H04L25/02; H04L25/20; H04L25/22

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 158 words
- Circuit for interfacing a half-duplex digital data line with a transmitting and a receiving lines, and vice-versa, characterized in that it includes: a multiple input coincidence gate (28) having a first input (32) connected directly to a receiving simplex line (34) and its output connected to a transmitting simplex line (30); a first time delay circuit (38A, 38B, 38C, 38D) connecting a second input of said gate (28) to said receiving simplex line (34) for causing a received simplex signal to be applied to said gate (28) after a first delay period; a second time delay circuit (42A, 42B, 42C) connecting a third input of said gate (28) to said receiving simplex line (34) for causing an inverted form of a received simplex signal to be applied to said gate (28) after a second delay period shorter than said first delay period, said second time delay circuit (42A, 42B, 42C) being connected to the half-duplex line (16).
Claim 2
Dependent Claim 158 words
- Circuit for interfacing a half-duplex digital data line with a transmitting and a receiving lines, and vice-versa, characterized in that it includes: a multiple input coincidence gate (28) having a first input (32) connected directly to a receiving simplex line (34) and its output connected to a transmitting simplex line (30); a first time delay circuit (38A, 38B, 38C, 38D) connecting a second input of said gate (28) to said receiving simplex line (34) for causing a received simplex signal to be applied to said gate (28) after a first delay period; a second time delay circuit (42A, 42B, 42C) connecting a third input of said gate (28) to said receiving simplex line (34) for causing an inverted form of a received simplex signal to be applied to said gate (28) after a second delay period shorter than said first delay period, said second time delay circuit (42A, 42B, 42C) being connected to the half-duplex line (16).
Claim 3
Dependent Claim 47 words
- A circuit as defined in claim 1, wherein said second time delay circuit (42A, 42B, 42C) includes at least two time delay elements (42B, 42C) connected in series and wherein the half-duplex line (16) is connected at a point intermediate two of said elements (42B, 42C).
Claim 4
Dependent Claim 57 words
- A circuit as defined in claim 2, wherein said first time delay circuit (38A, 38B, 38C, 38D) includes a plurality of time delay elements for establishing a delay period of 4T where T is a base delay time while said second time delay circuit (42A, 42B, 42C) includes elements for establishing a delay period of 3T.
Claim 5
Dependent Claim 31 words
- A circuit as defined in claim 3, wherein the time delay elements (42A, 42B) connecting the receiving simplex line (34) of the half-duplex line (16) provide a 2T delay period.

References Cited (Backward Citations)

DE1931162A1 Cited
FR2152599A1 Cited
US4154978A Cited

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