Selectable data throughput microprocessor system and heart pacemaker including same

Abstract

Abstract A microprocessor system comprises a central processor unit 99, a memory unit 100 and an input/output port 101, the central processor unit being provided with a high speed or burst clock 112 and low speed clock 113. Timing and control logic 104 is provided to select the clock used in the initiation of the execution of an instruction by the central processor unit, resulting in a variable delay between the execution of consecutive instructions. Thus, if the high speed clock 112 is selected, the instructions will be executed at a relatively high rate compared to that which will occur if the low speed clock 113 is selected. Selection of the clock rates is by special instructions causing the setting/resetting of a clock flag (H) in the processor status word 114 or by a special instruction selecting the high clock rate and loading a natural number into instruction counter 115, which number is decremented upon the execution of subsequent instructions so that when the stored number reaches zero the low clock rate is reselected, or by applying a logic level to timing and control logic 104 via control lead 116 from external logic hardware.

Inventors

• 👤 Ray Steven Mcdonald
• 👤 Martin Allan Rossing
• 👤 James Scott Nintzel

Bibliographic Details