EP0031672A2
Expired / Lapsed
EP
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An address buffer circuit
Assignee: Fujitsu Ltd
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Filing: 1980-12-17
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Granted: —
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Expires: 2000-12-17
Abstract
Abstract In a latch-type address buffer circuit for use in a clock-synchronous CMIS.RAM, a transistor 14 is connected between an inverter 11, 12, which is supplied with an address signal Ain, and a power source V D . A clock circuit 15 is provided for generating an internal clock signal by which only in the period of latching the input address signal A in, the transistor 14 is turned ON to make the inverter 11.12 operative thus reducing the total power consumption.
Inventors
- 👤 Hideo Itoh
- 👤 Kenji Agatsuma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 12:30
CPC Classifications
G; G11; G11C; G11C8/00; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
80 words
An address buffer circuit including an inverter to which an address signal is to be applied and a latch circuit to which an output signal from the inverter is to be applied, the address buffer circuit further comprising a transistor arranged to be connected between the inverter and a power source, and a clock circuit for generating an internal clock signal for turning ON the transistor only in the period of latching the input address signal in the latch circuit.
Claim 2
Dependent Claim
80 words
An address buffer circuit including an inverter to which an address signal is to be applied and a latch circuit to which an output signal from the inverter is to be applied, the address buffer circuit further comprising a transistor arranged to be connected between the inverter and a power source, and a clock circuit for generating an internal clock signal for turning ON the transistor only in the period of latching the input address signal in the latch circuit.
Claim 3
Dependent Claim
79 words
An address buffer circuit according to claim 1, wherein the clock circuit comprises a transistor which is arranged to operate in dependence on a signal inverted from an external clock signal to invert an output signal, a plurality of stages of inverters for delaying an internal clock signal for the latch circuit, derived from the external clock signal, and a further transistor for inverting the inverted output signal from the previous transistor by the output signal from the inverter.
Claim 4
Dependent Claim
100 words
An address buffer circuit including an inverter to which an address signal is to be applied and a latch circuit to which an output signal from the inverter is to be applied, the address buffer circuit further comprising a first transistor arranged to be connected between the inverter and a power source, a second transistor connected between the output terminal of the inverter and earth, and a clock circuit for generating an internal clock signal for turning ON the first transistor and OFF the second transistor only in the period of latching the. input address signal in the latch circuit.
Claim 5
Dependent Claim
100 words
An address buffer circuit including an inverter to which an address signal is to be applied and a latch circuit to which an output signal from the inverter is to be applied, the address buffer circuit further comprising a first transistor arranged to be connected between the inverter and a power source, a second transistor connected between the output terminal of the inverter and earth, and a clock circuit for generating an internal clock signal for turning ON the first transistor and OFF the second transistor only in the period of latching the. input address signal in the latch circuit.
References Cited (Backward Citations)
No citation records indexed.
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