Programmable sequential logic array mechanism

Claim 2

- Programmable sequential logic array mechanism for performing logical operations and solving logical equations, characterized in that it comprises: a search array subsystem for receiving a plurality of binary input signals and including an addressable storage array for supplying control words for testing for different input signal conditions and circuitry for producing output signals indicating the results of such tests; a read array subsystem for producing a plurality of binary output signals and including an addressable storage array for supplying output signal control words and circuitry responsive to the search array output signals for selecting the output signal control words which are allowed to determine the output signals; and address generating circuitry for generating a series of different storage addresses and for supplying each such address to the storage arrays in both the search array subsystem and the read array subsystem.

Claim 3

- Programmable sequential logic array mechanism for performing logical operations and solving logical equations, characterized in that it comprises: an input storage array having addressable plural-bit storage locations for storing input control words representing different logical combinations of binary input signals; input circuitry for receiving in parallel a plurality of binary input signals and for receiving input control words from the input storage array and producing binary truth signals indicating the states of agreement between the input signal conditions and the logical combinations represented by the input control words; a plurality of output register stages for providing a plurality of binary output signals; an output storage array having addressable plural-bit storage locations for storing output control words for controlling the states of the output register stages; address generating circuitry for sequentially generating a series of different storage addresses and for supplying each such address to the address circuitry of both the input and the output arrays; and control circuitry responsive to the truth signals produced by the input circuitry for enabling the output register stages to respond to selected output control words.

Claim 4

- Programmable sequential logic array mechanism for performing logical operations and solving logical equations, characterized in that it comprises: an input storage array having addressable plural-bit storage locations for storing input control words representing different logical combinations of binary input signals; input circuitry for receiving in parallel a plurality of binary input signals and for receiving input control words from the input storage array and producing binary truth signals indicating the states of agreement between the input signal conditions and the logical combinations represented by the input control words; a plurality of output register stages for providing a plurality of binary output signals; an output storage array having addressable plural-bit storage locations for storing output control words for controlling the states of the output register stages; address generating circuitry for sequentially generating a series of different storage addresses and for supplying each such address to the address circuitry of both the input and the output arrays; and control circuitry responsive to the truth signals produced by the input circuitry for enabling the output register stages to respond to selected output control words.

Claim 5

- Programmable sequential logic array mechanism in accordance with claim 2, characterized in that the input circuitry includes: circuitry for comparing each input signal with different bit position in an input control word for producing a comparison signal indicating the relative truth value of the input signal; and a logic circuit responsive to the various comparison signals for producing a binary truth signal indicating whether the various input signals as a group correspond to the logical conditions specified by the input control word.

Claim 6

- Programmable sequential logic array mechanism in accordance with. claim 2, characterized in that: each storage location in the input storage array includes two bit positions for each input signal; the input circuitry includes for each input signal a selector circuit followed by a compare circuit, with one input storage array bit position for each input signal being connected to a different one of the selector circuits and the other bit position for each input signal being connected to a different one of the compare circuits; and the input circuitry includes a logic circuit for receiving the output of all of the compare circuits and producing an output truth signal of predetermined truth value when the outputs of all of the compare circuits have an identical predetermined truth value.

Claim 7

- Programmable sequential logic array mechanism in accordance with claim 4, characterized in that each selector circuit is an AND circuit, each compare circuit is an EXCLUSIVE OR circuit and the logic circuit is an AND circuit.

Claim 8

- Programmable sequential logic array mechanism in accordance with claim 2, characterized in that the input circuitry includes circuitry for providing plural-bit partitioning of the input signals.

Claim 9

- Programmable sequential logic array mechanism in accordance with any of the preceding claims characterized in that the address generating circuitry is comprised of an address counter driven by a free-running clock pulse generator.

Claim 10

- Programmable sequential logic array mechanism in accordance with claim 7, characterized in that: the input signals are divided into groups; a multiplexer circuit is provided for each group of input signals; the input signals of each group are supplied to the select inputs of its multiplexer circuit; the input storage array supplies to the data inputs of each multiplexer a plurality of signals representing different product term combinations for the input signals in such group; and the outputs of the various multiplexer circuits are connected to a logic circuit which produces for each input control word a binary truth signal indicating the state of agreement between the various input signal conditions and the logical combination represented by the input control word, the various successive binary truth signals produced by this logic circuit being the truth signals to which the control circuitry is responsive.

Claim 11

- Programmable sequential logic array mechanism in accordance with claim 7, characterized in that it further comprises: four-to-one multiplexer circuits, each such multiplexer circuits being provided with two select input terminals, four data terminal inputs and a data output terminal; the two select input terminals of a four-to-one multiplexer circuit receiving a different pair of input signals; the four data terminal inputs of each multiplexer circuit receiving a different group of four control word output lines of the input storage array; and the data output terminals of the different multiplexer circuits being coupled to a logic circuit for producing the binary truth signals to which the control circuitry is responsive.

Claim 12

- Programmable sequential logic array mechanism in accordance with claim 2 or 8 or 9, characterized in: circuitry for time multiplexing input signals into the input circuitry; and circuitry for synchronizing the addressing of the input and output storage arrays with the input signal multiplexing for providing different input and output control words for each set of the time multiplexed input signals.

Claim 13

- Programmable sequential logic array mechanism in accordance with-claim 10, characterized in that: an additional multiplexer circuit is provided for each input signal, the data output terminal of each such additional multiplex circuit delivering a different input signal and the N data input terminals of each such multiplexerer circuit reeeiving different signals which are time multiplexed onto an input signal on the data output terminal; the control words in the input and output storage arrays are organized in groups of N successive control words, the different control words in each group corresponding to the different ones of the N sets of signals which are multiplexed by the additional multiplexer circuits; and the control circuitry includes circuitry for detecting for each repetition of the multiplexing of the N sets of input signals the occurrence of N successive truth signals of the same predetermined truth value for enabling groups of output register stages to respond to different ones of the control words in the corresponding group of N output control words.

Claim 14

- Programmable sequential logic array mechanism in accordance with claim 11, characterized in that the control circuitry further includes circuitry responsive to the occurrence of a truth signal having a value opposite to the predetermined value for resetting the multiplexing sequence and for advancing the address generating circuitry to the starting address for the next group of N control words.