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EP0029975A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Multiprocessor system

Assignee: Bull HN Information Systems Italia SpA
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Filing: 1980-11-21
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Granted: —
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Expires: 2000-11-21
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Abstract

Abstract In a multiprocessor system comprising a plurality of processors (1, 2, 3) and a memory unit (4), connected each other through a common bus (6), each processor communicates with the memory through the bus. Communication among processors is also effected by storing in memory, into zones, each dedicated to one processor but accessible to all the processors, the messages intended for the several processors. <??>This operation is performed using the common bus and the normal memory communication procedure. <??>Once this operation is performed a notify signal is sent on the common bus and identified by the only processor it is intended for. <??>The notify signal is memorized by the notified processor without interrupting its going on operation and it is taken into account in a completely autonomous way as to the notifying processor. <??>The identification of the notify signal causes the notified processor to subsequently access the memory unit and the readout of the message.

Inventors

  • 👤 Angelo Bardotti

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 03:19
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 214 words
1 . A multiprocessor system comprising a plurality of processors and a memory unit, connected each other through a common bus, to which each processor can access for information exchange with said memory unit, characterised by that: A) the memory unit comprises: a plurality of storage resources, having initial fixed memory addresses each one related to one processor and accessible to all the processors, for receiving and storing messages intended for the related processor, B) each processor comprises: - first means for generating signals representative of its own proces sor name, - second means for loading said bus with sighals representative of the name of a notified processor to which messages are intended to be notified, - third means for receiving through said bus signals representative of the name of a notified processor, - a comparator coupled to said first and third means for receiving and comparing its own processor name with said notified processor name and for producing a notify signal when said names are equal, - inconditioned storing means for said notify signal so that the noti fied processor is autonomously able to recognize said notify signal in said inconditioned storing means and to receive the messages intended for it and previously stored into its own related resources within the memory unit.
Claim 2
Dependent Claim 214 words
1 . A multiprocessor system comprising a plurality of processors and a memory unit, connected each other through a common bus, to which each processor can access for information exchange with said memory unit, characterised by that: A) the memory unit comprises: a plurality of storage resources, having initial fixed memory addresses each one related to one processor and accessible to all the processors, for receiving and storing messages intended for the related processor, B) each processor comprises: - first means for generating signals representative of its own proces sor name, - second means for loading said bus with sighals representative of the name of a notified processor to which messages are intended to be notified, - third means for receiving through said bus signals representative of the name of a notified processor, - a comparator coupled to said first and third means for receiving and comparing its own processor name with said notified processor name and for producing a notify signal when said names are equal, - inconditioned storing means for said notify signal so that the noti fied processor is autonomously able to recognize said notify signal in said inconditioned storing means and to receive the messages intended for it and previously stored into its own related resources within the memory unit.
Claim 3
Dependent Claim 83 words
2 . A multiprocessor system as claimed in claim 1 wherein each processor further comprises: first circuit means for generation of an ENCY signal on a bus lead, for terminating the exchange of information signals among processors, in the course of an interprocessor transfer of the name of a notified processor and wherein said memory unit further comprises second circuit means for inhibiting the activation of a memory cycle in the course of an interprocessor transfer of the name of a notified processor.

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