Receiver for push-button PCM-encoded multifrequency signals

Claim 2

1) Receiver for push-button PCM-encoded multifrequency signals, characterized in that it consists of two band-split digital filters (FA, FB) followed by two circuits designed to control the level of the signal produced by said filters and by-two interpolator limiter circuits (SIA, SIB) to whose outputs a circuit (CR) recognizing the digit transmitted by means of said multifrequency signals is connected, said limiter-interpolator circuits (SIA, SIB) being apt to determine the instant of passage through zero of the analogic waveforms from which the PCM encoded multifrequency signal has been obtained.

Claim 3

2) Receiver for push-button PCM-encoded multifrequency signals as in claim 1, characterized in that each of said limiter-interpolator circuits (SIA, SIB) consists of: a register (RX) of parallel type apt to operate as delay line on the samples received for a time equal to a sampling period (T c ); a sign separating circuit (S), connected before said register (RX), apt to determine the sign of the received sample; an interpolating network (RI) connected by means of a first (MI) and a second (M2) modulus separating circuit respectively before and after said register (RX), apt to effect, at each sampling interval (Tc), on two samples, present the one before (x n -1) and the other after (x n ) the register, a linear interpolation according to the expression: in which: I denotes that it has to be taken the integer part of what is bracketed; N oa is the product of the interpolation; N is the ratio between the frequency (f cv ) of clock signal (CK) and the sampling frequency (f c ); |x n-1 |is the value of the sample modulus after the register; I x n |is the value of the sample modulus before the register; - a pulse generator circuit (GP) able to generate a pulse of duration equal to the period (T CV ) of the clock signal (CK) whenever at its input, connected to the output of said sign separator (S), there is a variation in the logic level, - a logic comparator (CMP) with two inputs and one output, a synchronous counter (C) with modulus N and a sequential logic network (RS) able to cooperate to keep the logic value "I" on the external output (10) of said sequential logic network (RS) beginning at the instant at whichthepulseis generated by said pulse generating circuit (GP), connected to one of the inputs of said sequential logic network (RS), and for a duration equal to N oa . T CV · - a logic gate (P) of EX-OR type able to produce on its output and on the output of the receiver the esclusive OR of the logic value present on the external output (10) of said sequential logic network (RS) and of the logic value coming from said sign separator (S).

Claim 4

3) Receiver for push-button PCM-encoded multifrequency signal receiver as in claim 2, characterized in that the interpolation product computed by said interpolation network (RI) is equal to N oa only when said samples before (x n _ 1 ) and after (x n ) said register (RX) have opposite sign.

Claim 5

4) Multifrequency PCM-encoded push-button signal receiver, the whole as described in the text and depicted in the annexed drawings.

Claim 6

4) Multifrequency PCM-encoded push-button signal receiver, the whole as described in the text and depicted in the annexed drawings.