Training circuit for audio signal recognition computer

Claim 2

Apparatus for signal pattern recognition, characterised by means (114) for storing a reference data pattern; means (36) for comparing a signal pattern with said reference pattern for recognition; and means (34) for updating said reference data pattern comprising means (110) for inputting a training signal pattern; means (116) for comparing said training signal pattern with said reference data pattern-to generate a score signal indicative of the similarities therebetween; means (130) for combining said reference data pattern with said training pattern to produce a new reference data pattern; and means (122) for replacing said reference data pattern with said new reference data pattern in said storing (114) means if said score signal exceeds a predetermined level.

Claim 3

Apparatus for signal pattern recognition, as claimed in claim 1, wherein said updating means (34) further comprises means (124,136) for adjusting said predetermined level.

Claim 4

Apparatus for signal pattern recognition as claimed in claim 2 wherein said predetermined level adjusting means comprises means (124) for counting the number of said training signal patterns which have been combined by said combining means (130) to produce said reference data pattern; arid means (322) for setting said predetermined level as a function of the output count of said counting means.

Claim 5

Apparatus for signal pattern recognition as claimed in claim 3 wherein said setting means (322) increases said predetermined level in response to an increased count output from said counting means (124).

Claim 6

Apparatus for signal pattern recognition as claimed in claim 3 wherein said setting means (322) comprises a read only memory.

Claim 7

Apparatus for signal pattern recognition as claimed in claim 1, wherein said updating means (34) further comprises means (124) for counting sequential training signal patterns which produce score signals from said comparing means below a predetermined level; and means (126,128) responsive to said counting means for initiating additional training of said reference data pattern.

Claim 8

Apparatus for signal pattern recognition as claimed in claim 6 wherein said initiating means (126,128) comprises means (114) for storing a number equal to the number of training signal patterns previously combined in said combining means to produce said reference data pattern; means (134) for operating said training signal pattern inputting means (110) in response to said number of previously combined training signals; and means (128) for setting said number of training signal patterns in said storing means (114) to a lower value in response to said counting means (124).

Claim 9

Apparatus for signal pattern recognition as claimed in claim 7 wherein said setting means (128) sets said number of training signal patterns in said storing means (114) to zero.

Claim 10

Apparatus for signal pattern recognition, characterized by means (114) for storing plural reference data patterns; means (110,116) for inputting and comparing a training signal pattern with said plural reference data patterns for recognition; means (130) for combining a plurality of training signal patterns to produce each of said plural reference data patterns; and means (124,134,138) for controlling said inputting and combining means to combine the identical number of training signal patterns for each of said plural reference data patterns.

Claim 11

Apparatus for signal pattern recognition, characterized by means (114) for storing plural reference data patterns; means (110,116) for inputting and comparing a training signal pattern with said plural reference data patterns for recognition; means (130) for combining a plurality of training signal patterns to produce each of said plural reference data patterns; and means (124,134,138) for controlling said inputting and combining means to combine the identical number of training signal patterns for each of said plural reference data patterns.

Claim 12

Apparatus for signal pattern recognition as claimed in claim 9 wherein said controlling means comprises means (124,344) for storing a number equal to the number of training signal patterns previously combined in said means to produce said reference data pattern; means (251) for storing a desired number of training signal patterns; means (354) for comparing said stored number of previously combined training signal patterns with said stored desired number of training signal patterns; and means (138,360) responsive to said comparing means for controlling said inputting and combining means.

Claim 13

Apparatus for signal pattern recognition comprising: a memory (114) storing multiple reference data patterns; means (116) for comparing said signal patterns against said multiple reference data patterns for recognition; and a circuit (34) for storing said multiple reference data patterns in said memory, comprising: means (10) for inputting and storing new signal patterns for cumulative use in generating one of said multiple reference data patterns; means (130) for combining said new signal patterns with said one reference data pattern previously stored in said memory (114) to produce a new reference data pattern; means (220) for replacing said one reference data pattern previously stored with said new reference data pattern in said memory (114); and means (124,134,138) for sequencing said inputting and storing means to assure that said inputting, combining and merging means operate an identical number of times on each of said multiple reference data patterns in said memory.

Claim 14

Apparatus for signal pattern recognition comprising: a memory (114) storing multiple reference data patterns; means (116) for comparing said signal patterns against said multiple reference data patterns for recognition; and a circuit (34) for storing said multiple reference data patterns in said memory, comprising: means (10) for inputting and storing new signal patterns for cumulative use in generating one of said multiple reference data patterns; means (130) for combining said new signal patterns with said one reference data pattern previously stored in said memory (114) to produce a new reference data pattern; means (220) for replacing said one reference data pattern previously stored with said new reference data pattern in said memory (114); and means (124,134,138) for sequencing said inputting and storing means to assure that said inputting, combining and merging means operate an identical number of times on each of said multiple reference data patterns in said memory.

Claim 15

A signal pattern encoder and classifier comprising: a transducer (10); a signal processing means (12,14,16,18,20,22) coupled to the output of said transducer (10) for providing spectrum samples representative of the signal output of said transducer; event encoding logic means (24,116) coupled to the output of said signal processing means for computing the difference between a current spectrum sample and the last previous spectrum sample accepted by said event encoding logic means; means (122) responsive to said event encoding means (24,116) for rejecting said current spectrum sample if said difference is below a predetermined value; timing and control means (40) coupled to said signal processing means and said event encoding logic means; reference pattern memory means (26,114) coupled with said timing and control means; and pattern classification means connected to said event encoding means, said timing and control means and said reference pattern memory wherein said pattern classification means comprises: means (134,344,350,354) for notifying the apparatus user to submit additional data; means (240,242) responsive to said notification means for causing samples to be taken of the additional data; means (10,12,14,16,18,20,22,24,27) responsive to incoming samples for comparison and coding for those samples; storage means (26) connected to said comparison and coding means for storing the coded data; means (112,116) connected to said reference pattern memory (114) for comparison of incoming data and assigning a comparison value to said incoming data; means (118,122) responsive to said assigned comparison value for determining whether the particular coded incoming data sample is acceptable above a predetermined threshold value; and means (130) responsive to said determining means and connected to said reference pattern memory for storing said incoming data sample into said reference pattern memory.

Claim 16

A signal pattern encoder and classifier comprising: a transducer (10); a signal processing means (12,14,16,18,20,22) coupled to the output of said transducer (10) for providing spectrum samples representative of the signal output of said transducer; event encoding logic means (24,116) coupled to the output of said signal processing means for computing the difference between a current spectrum sample and the last previous spectrum sample accepted by said event encoding logic means; means (122) responsive to said event encoding means (24,116) for rejecting said current spectrum sample if said difference is below a predetermined value; timing and control means (40) coupled to said signal processing means and said event encoding logic means; reference pattern memory means (26,114) coupled with said timing and control means; and pattern classification means connected to said event encoding means, said timing and control means and said reference pattern memory wherein said pattern classification means comprises: means (134,344,350,354) for notifying the apparatus user to submit additional data; means (240,242) responsive to said notification means for causing samples to be taken of the additional data; means (10,12,14,16,18,20,22,24,27) responsive to incoming samples for comparison and coding for those samples; storage means (26) connected to said comparison and coding means for storing the coded data; means (112,116) connected to said reference pattern memory (114) for comparison of incoming data and assigning a comparison value to said incoming data; means (118,122) responsive to said assigned comparison value for determining whether the particular coded incoming data sample is acceptable above a predetermined threshold value; and means (130) responsive to said determining means and connected to said reference pattern memory for storing said incoming data sample into said reference pattern memory.

Claim 17

A signal pattern encoder as claimed in claim 12 wherein said threshold value is varied automatically (136) in response to the number of incoming samples used to generate the data in said reference pattern memory.

Claim 18

A signal pattern encoder as claimed in claim 12, further comprising second storage means (114,348) retaining a history of incoming samples tested; and third storage means (124) retaining a history of samples not meeting said predetermined threshold value.

Claim 19

A signal pattern encoder as claimed in claim 14 wherein said pattern classification means further comprises means (126,124,132) responsive to said third storage means for discarding data in said reference pattern memory.

Claim 20

A signal pattern encoder as claimed in claim 14 wherein said pattern classification means further comprises means (136) responsive to said second storage means for varying said predetermined threshold.