Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
90 words
A signal converter circuit, wherein n memory elements are arranged for holding respective values of an input signal fed to the converter circuit, the respective values being the value of the input signal at a present clock timing instant and the values of the input signal at n-1 clock timing instants preceding the present clock timing instant, and wherein means are provided for deriving an output signal value, for an output signal fed from the converter circuit, equal to 1/n the sum of the values held in the memory elements.
Claim 2
Dependent Claim
90 words
A signal converter circuit, wherein n memory elements are arranged for holding respective values of an input signal fed to the converter circuit, the respective values being the value of the input signal at a present clock timing instant and the values of the input signal at n-1 clock timing instants preceding the present clock timing instant, and wherein means are provided for deriving an output signal value, for an output signal fed from the converter circuit, equal to 1/n the sum of the values held in the memory elements.
Claim 3
Dependent Claim
46 words
A circuit as claimed in claim 1, wherein the means for deriving an output signal value include an adder arranged for adding together the values held in the memory elements, and a divider for dividing by n the result of the addition effected by the adder.
Claim 4
Dependent Claim
58 words
A circuit as claimed in claim 1, wherein n=2 N and input signal values are digital, and wherein the means for deriving an output signal value derive that value by addition of the input signal values held in the memory elements after bit shifting by N bits, thereby effectively to divide the input signal values by 2 .
Claim 5
Dependent Claim
32 words
A circuit as claimed in claim 1, 2 or 3, wherein the n memory elements are cascade-connected to form a shift register, to one end of which the input signal is fed.
Claim 6
Dependent Claim
31 words
A circuit as claimed in claim 1, 2 or 3, further comprising a scanner arranged to scan the input signal and write the respective input signal values into the memory elements.
Claim 7
Dependent Claim
33 words
Numerical control apparatus, having a signal anverter circuit as claimed in any preceding claim, arranged for receiving as the input signal for the converter circuit a signal indicating a desired amount of movement.