Semiconductor memory device including integrated injection logic memory cells

Claim 2

A semiconductor integrated circuit device comprising: a plurality of word lines (W , W 1 , ... w n-1 ; Fig 10); a plurality of word drivers, each connected to one of the word lines; a plurality of hold lines (H o , H 1 , ..., H n-1 ); a plurality of pairs of bit lines (B o , B o ; B 1 , B 1 ; ...; B n-1 , B n-1 ); a plurality of bit drivers, each connected to one of the pairs of bit lines; a plurality of memory cells of integrated injection logic (C oo , C o1 , ..., C n-1,n-1 ) to one of the hold lines and to one of the pairs of bit lines; and characterized by a means which selectively alters the lower one of the two potentials of a selected pair of bit lines in response to the read mode and the write mode, the said lower potential during the read mode being higher than it is during the write mode.

Claim 3

A device according to claim 1, wherein the said altering means comprises: a plurality of clamp transistors (Q co , Fi g. 7), each of whose emitters is connected to one of the pairs of bit lines; and a current switching circuit (CS1) for selectively clamping the gates of the clamp transistors in response to a write enable signal (WE).

Claim 4

A device according to claim 2, wherein the current switching circuit (CS1, Fig. 7) comprises: a current switch comprising two transistors (Q 9 , Q10) controlled by the said write enable signal (WE) and a reference voltage (V R ), respectively; a current source (I c ) for supplying a current to the current switch; and a resistor (R 3 ) connected to one of the two transistors.

Claim 5

A device according to claim 1, wherein the said altering means comprises: a plurality of pairs of clamp transistors (Q Ao , Q Bo ; Fig.8), each pair connected to one of the pairs of bit lines; and a current switching circuit (CS2) for selectively clamping the bases of the clamp transistors in response to a write enable signal (WE) and an input data signal (D in ).

Claim 6

A device according to claim 4, wherein the current switching circuit comprises: a first current switch comprising two transistors (Q 11 , Q 12 ) controlled by the input data signal (Din) and a first reference voltage (V R1 ); a second current switch comprising a further three transistors (Q13, Q 14 , Q15), of which two transistors (Q13, Q14) are controlled by the write enable signal,(WE),and the third transistor (Q 15 ) is controlled by a second reference voltage (V R2 ) and is connected to the first current switch; a current source (I c ) for supplying current to the second current switch; a pair of resistors (R 4 , R 5 ) each connected to a different one of the two transistors (Q 11 , Q 12 ) of the first current switch; and a pair of diodes (D 1 , D 2 ) connected in series with opposite conducting directions, the connection point of the diodes being connected to one of the said two transistors (Q13, Q14) in the second current switch.controlled by the write enable signal.

Claim 7

A device according to claim 4 or 5, comprising an additional clamp circuit which includes: a plurality of pairs of clamp transistors (Q D , Q E ; Fig 10), each pair connected to its associated pair of bit lines; a plurality of clamp resistors (R), each one connected to a reference potential (V 1 co , Fig. 10) and to both gates of one pair of clamp transistors (Q D , Q E ); and a plurality of switching transistors (Q Fo , Q Fl ), ..., Q Fn-1 ), each connecting an additional common current source (I c ) to both gates of one pair of clamp transistors when its associated bit column is selected.

Claim 9

A device according to claim 7, wherein each differential read-out circuit is driven by a driving transistor (Q So , Q Sl ..., Q Sn-1 ) connected to a common current source (I o ), and wherein the gates of the driving transistor, the switching transistor, and the bit drivers are all connected together and are supplied with a column selection signal (V , V yl , ... V yn-1 ).