EP0023254A2 — Method and apparatus for controlling power distri…

Claim 1

Independent Claim 106 words

A method for controlling the distribution of power along power lines of an electric utility from a substation to a plurality of loads, characterized by: (a) generating master control signals under control of a programmable digital data processor; (b) communicating said control signals to a substation injection unit located at said substation; (c) injecting pulse code signals onto said power lines under control of a second programmable digital processor in response to said control signals; and (d) operating at least one of a plurality of remote receiver units in response to said pulse code signals to connect or disconnect a load from said . power lines.

Claim 2

Independent Claim 106 words

A method for controlling the distribution of power along power lines of an electric utility from a substation to a plurality of loads, characterized by: (a) generating master control signals under control of a programmable digital data processor; (b) communicating said control signals to a substation injection unit located at said substation; (c) injecting pulse code signals onto said power lines under control of a second programmable digital processor in response to said control signals; and (d) operating at least one of a plurality of remote receiver units in response to said pulse code signals to connect or disconnect a load from said . power lines.

Claim 3

Dependent Claim 37 words

Method of Claim 1 characterized in that said injecting step comprises converting the frequency of a standard power line voltage signal generated by said utility at said substation to a preselected frequency for said pulse code signals.

Claim 4

Dependent Claim 93 words

Method of Claims 1 or 2 characterized in that said communication step provides two-way communications and in that said generation of master control signals includes polling each of said substation injection units to obtain information pertaining to its status,possible ala.rm conditions, and analog or discrete data generated at the respective substation; transmitting and receiving serial binary block messages to and from each of said substation injection units, said block messages including substation injection unit address data, substation injection unit function commands and said data signals; and prioritizing and executing said group control commands.

Claim 5

Dependent Claim 147 words

Apparatus for controlling the distribution of power along power lines of an electric power utility from a substation to a plurality of loads, characterized by: a master control station including first programmable digital data processor means and input/output devices under the control of an operator for generating master control signals; at least one substation injection unit located at said substation in communication with said master control station and operating under the control of second programmable digital data processor means for injecting, in response to certain of said master control signals, pulse code signals onto said power lines; and a plurality of remote receiver units each connected to a particular load device and to said power lines for receiving said pulse code signals, each of said remote receiver units being responsive to one of said pulse code signals for connecting or disconnecting its load from said power lines.

Claim 6

Dependent Claim 147 words

Apparatus for controlling the distribution of power along power lines of an electric power utility from a substation to a plurality of loads, characterized by: a master control station including first programmable digital data processor means and input/output devices under the control of an operator for generating master control signals; at least one substation injection unit located at said substation in communication with said master control station and operating under the control of second programmable digital data processor means for injecting, in response to certain of said master control signals, pulse code signals onto said power lines; and a plurality of remote receiver units each connected to a particular load device and to said power lines for receiving said pulse code signals, each of said remote receiver units being responsive to one of said pulse code signals for connecting or disconnecting its load from said power lines.

Claim 7

Dependent Claim 83 words

Apparatus of Claim 4, characterized in that said substation injection unit further comprises: means for converting the frequency of a standard power line voltage signal generated by said utility at said substation to a preselected frequency for said pulse code signals; means responsive to said second data processor means for controlling the output of said frequency converting means to generate said pulse code signals; and means for injecting said pulse code signals onto said power lines for transmission to said remote receiver units.

Claim 8

Dependent Claim 96 words

Apparatus of Claims 4 or 5 characterized in that said frequency converting means comprises: three-phase rectifier means including a plurality of conduction-controlled solid state devices underline control of said second data processor means for receiving said three-phase power line voltage signal and for developing a DC voltage signal of a predetermined level; and three-phase inverter means including a plurality of conduction-controlled solid state devices under the control of said second data processor means for receiving said DC voltage signal from said rectifier means and for converting same to said pulse code signal at said preselected frequency.

Claim 9

Dependent Claim 120 words

Apparatus of Claims 4, 5 or 6 characterized in that said means for controlling the output of said frequency converting means comprises: means for controlling the firing time of said solid state devices in said three-phase rectifier means to select one of a plurality of output voltage levels as said predetermined level; and means for controlling the firing time and sequence of said solid state devices in said three-phase inverter means to establish an idle mode and an inject mode for said inverter means, said idle mode corresponding to the absence of a pulse in said pulse code signals, and . said inject mode corresponding to the presence of a pulse in said pulse code signals at said preselected frequency.

Claim 10

Dependent Claim 87 words

Apparatus of Claim 6 or 7 characterized in that said means for controlling the firing time of said solid state devices in said three-phase rectifier means includes: means for receiving the three-phase voltage waveform from said power line; means for determining when each of said voltage waveforms is greater than the other two waveforms and for providing output signals thereupon; and means responsive to said output signals of said determining means for turning on and off the gates of said solid state devices in said rectifier means.

Claim 11

Dependent Claim 78 words

Apparatus of any one of Claims 5-8 characterized in that said injecting means comprises: transformer means whose primary is connected to receive said pulse code signals for transforming the relatively low voltage current thereof to a higher voltage and current for injection onto said power lines; and tuned circuit means connected to the secondary of said transformer means and tuned to said preselected frequency for passing said pulse code signals to the power output bus of said substation.

Claim 12

Dependent Claim 92 words

Apparatus of any one of Claims 6-9 further characterized by: input power contactor means connected in series with said rectifier means for connecting and disconnecting same to said three-phase power line voltage signal; output power contactor means connected in series with said inverter means for connecting and disconnecting same to said power lines; power breaker means connected in series with said input and output power contactor means and including a shunt trip circuit responsive to fault conditions for tripping said power breaker means and opening said input and output power contactor means.

Claim 13

Dependent Claim 83 words

Apparatus of any one of Claims 6-10 characterized in that said inverter means includes: first temperature detector means for sending an alarm signal to said second data processor means upon sensing a first temperature level of said solid state devices; and second temperature detector means for actuating said power breaker means upon sensing a second temperature level of said solid state devices higher than said first temperature level for disabling said substation injection unit by opening said input and output power contactor means.

Claim 14

Dependent Claim 30 words

Apparatus of any one of Claims 4-11 characterized in that said second data processor means includes means for controlling communications between said master control station and said substation injection unit.

Claim 15

Dependent Claim 71 words

Apparatus of any one of Claims 4-12 characterized in that said substation injection unit further comprises: analog input means for connecting one or more inputs at said substation indicative of one or more analog system parameters for transmission to said master control station; and discrete input means for connecting one or more inputs at said substation indicative of one or more discrete system parameters for transmission to said master control station.

Claim 16

Dependent Claim 55 words

Apparatus of any one of Claims 4-13 characterized in that said substation injection unit further comprises: means connected to said power lines for detecting each pulse in said pulse code signals; and means in said second data processor means for determining whether the outputs of said pulse detecting means consist of a properly timed pulse.

Claim 17

Dependent Claim 109 words

Apparatus of any one of Claims 4-14 characterized in that said plurality of substation injection units are in two-way communication with said master control station, and in that said master control station includes: means for polling each of said substation injection units to obtain information pertaining to its status, possible alarm conditions, and analog or discrete data generated at the respective substation; means for transmitting and receiving serial binary block messages to and from each of said substation injection units, said block messages including substation injection unit address data, substation injection unit function commands and said data signals; and means for prioritizing and. executing said group control commands. i

Claim 18

Dependent Claim 68 words

Apparatus of any one of Claims 4-15 further characterized by means connected to said second data processor means for receiving an indication of the desired output voltage level of said rectifier means; and time delay means connected to said determining means and said voltage level receiving means for delaying said output of said determining means for a period of time in accordance with said desired output voltage level.

Claim 19

Dependent Claim 96 words

Apparatus of any one of Claims 7-16 characterized in that said means for controlling the firing time and sequence of said solid state devides in said three-phase inverter means comprises: first means responsive to a mode select address signal from said second data processor means for selecting either said idle mode or said inject mode; second means responsive to said first means ,for generating register output timing signals; and register means responsive to said first and second means for providing gate signals in a predetermined order to said solid state devices in said three-phase rectifier means.'

Claim 20

Dependent Claim 41 words

Apparatus of any one of Claims 10-17 further characterized by means for sensing fault conditions including means for sensing overcurrent in the output of said rectifier means, and means for sensing short circuits across the DC bus of said inverter means.

Claim 21

Independent Claim 128 words

A method for controlling the distribution of power along power lines of an electric utility characterized by the steps of: arranging a plurality of loads into individually controllable load control groups; establishing first, second and third types of control lists, each of said lists including at least one group control command for causing one of said load control groups to be turned on or off; actuating said first type of control list upon command to execute its group control commands once; actuating said second type of control list upon command to execute its group control commands cyclically and repetitively; and actuating said third type of control list upon command to execute its group control commands cyclically and repetitively while taking into account the power demand on said utility.

Claim 22

Independent Claim 128 words

A method for controlling the distribution of power along power lines of an electric utility characterized by the steps of: arranging a plurality of loads into individually controllable load control groups; establishing first, second and third types of control lists, each of said lists including at least one group control command for causing one of said load control groups to be turned on or off; actuating said first type of control list upon command to execute its group control commands once; actuating said second type of control list upon command to execute its group control commands cyclically and repetitively; and actuating said third type of control list upon command to execute its group control commands cyclically and repetitively while taking into account the power demand on said utility.

Claim 23

Dependent Claim 68 words

The method of Claim 19 further characterized by the step of dynamically adjusting the on and off times of the loads in those of said control groups belonging to said third type of control list by monitoring the utility's system power demand and lengthening the off times of said loads as said power demand increases in those of said control groups in said third type of control list.

Claim 24

Dependent Claim 64 words

The method of Claim 19 or 20 further characterized by the steps of establishing a load profile table indicative of the anticipated total power demand at predetermined intervals of time, and adjusting the on and off times of the loads in those of said control groups belonging to said third type of control list by comparing the actual time with the load profile table.

Claim 25

Dependent Claim 76 words

The method of Claim 19, 20 or 21 further characterized by the steps of: periodically scanning each of said control lists to determine whether it should be activated or deactivated; periodically checking each of said group control commands in those of said lists that are activated to determine whether the command should be carried out, and generating data signals for those of said activated group control commands when it is time to carry out said command.

Claim 26

Independent Claim 188 words

A method of injecting a pulse code signal onto power lines of an electric utility for controlling the distribution of power along said power lines characterized by the steps of: (a) transmitting a first binary injecting message representing said desired control command from said master control station to each of said plurality of substation injection units in turn; (b) transmitting a second binary injection message representing said desired control command received in step (a) from each of said substation injection units in turn to said master control station; (c) verifying at said master control station that said second binary message is the same as _said first binary message; (d) transmitting a binary commence keying command signal from said master control station to all of said substation injection units simultaneously; (e) generating a pulse code signal representing said first binary injection message at each of said substation injection units verified by step (c); and (f) injecting said pulse code signal generated in step (e) onto the utility's power lines for transmission to a plurality of coded receiver units remotely located at said loads to effect said desired control command.

Claim 27

Independent Claim 188 words

A method of injecting a pulse code signal onto power lines of an electric utility for controlling the distribution of power along said power lines characterized by the steps of: (a) transmitting a first binary injecting message representing said desired control command from said master control station to each of said plurality of substation injection units in turn; (b) transmitting a second binary injection message representing said desired control command received in step (a) from each of said substation injection units in turn to said master control station; (c) verifying at said master control station that said second binary message is the same as _said first binary message; (d) transmitting a binary commence keying command signal from said master control station to all of said substation injection units simultaneously; (e) generating a pulse code signal representing said first binary injection message at each of said substation injection units verified by step (c); and (f) injecting said pulse code signal generated in step (e) onto the utility's power lines for transmission to a plurality of coded receiver units remotely located at said loads to effect said desired control command.

Claim 28

Dependent Claim 92 words

The method of Claim 23 further characterized by the steps of: (g) positioning a receiver unit in each of said substation injection units for receiving, on a pulse-by-pulse basis, the pulse code signal injected by step (f); (h) storing the outputs of each of said receiver units in its respective substation injection unit until the full pulse code signal has been injected; and (i) transmitting said stored outputs from each of said substation injection units to said master control station in turn to verify that said desired control command has been effected.

Claim 29

Dependent Claim 123 words

Method for controlling the firing time and sequence of gated conduction-controlled rectifiers in an inverter characterized by the steps of: (a) providing a portion of address information on an address bus in response to functional commands indicative of the desired mode of operation of said inverter; (b) generating next address information from a first memory in response to said address information; (c) receiving said next address information in a first register and delivering the other portion of y said address information to said address bus; (d) generating next gate control signals from a second memory in response to said address information; (e) receiving said next gate control signals in a second register and providing signals for the gate controlled rectifiers of said inverter.

Claim 30

Dependent Claim 123 words

Method for controlling the firing time and sequence of gated conduction-controlled rectifiers in an inverter characterized by the steps of: (a) providing a portion of address information on an address bus in response to functional commands indicative of the desired mode of operation of said inverter; (b) generating next address information from a first memory in response to said address information; (c) receiving said next address information in a first register and delivering the other portion of y said address information to said address bus; (d) generating next gate control signals from a second memory in response to said address information; (e) receiving said next gate control signals in a second register and providing signals for the gate controlled rectifiers of said inverter.

Claim 31

Dependent Claim 140 words

An inverter controller for controlling the firing time and sequence of gated conduction-controlled rectifiers characterized by: an address bus for providing address information; means responsive to functional commands indicative`of the desired mode of operation of said inverter for providing a portion of said address - information on said address bus; first memory means responsive to said address information on said address bus for generating next address information; first register means for receiving said next address information from said first memory means and for delivering the other portion of said address information to said address bus; second memory means responsive to said address information on said address bus for generating next gate control signals; and second register means for receiving said next gate control signals from said second memory means for providing signals for the gate controlled rectifiers of said inverter.

Claim 32

Dependent Claim 140 words

An inverter controller for controlling the firing time and sequence of gated conduction-controlled rectifiers characterized by: an address bus for providing address information; means responsive to functional commands indicative`of the desired mode of operation of said inverter for providing a portion of said address - information on said address bus; first memory means responsive to said address information on said address bus for generating next address information; first register means for receiving said next address information from said first memory means and for delivering the other portion of said address information to said address bus; second memory means responsive to said address information on said address bus for generating next gate control signals; and second register means for receiving said next gate control signals from said second memory means for providing signals for the gate controlled rectifiers of said inverter.

Claim 33

Dependent Claim 59 words

The inverter controller of Claim 26, further characterized by means for receiving clock signals and for generating a plurality of timing signals, said first and second register means being responsive to certain of said timing signals to enable receipt thereby of said next address information and said next gate control signals respectively from said first and second memory means.

Claim 34

Dependent Claim 72 words

The inverter controller of Claim 26 or 27 characterized in that said means responsive to functional commands comprises: mode select register means for receiving said functional commands upon receipt thereby of one of said clock signals and for developing a binary mode select signal in response thereto; and mode control register means for receiving said mode select signal upon receipt thereby of a first timing signal and an enable mode change signal.

Claim 35

Dependent Claim 60 words

The inverter controller of Claim 28 characterized in that said second memory means is further responsive to said address information for generating said enable mode change signal, said second register means connected to receive said enable mode change signal and to send same to said mode control register means upon receipt of one of a series of second timing signals.

Claim 36

Dependent Claim 66 words

.30. The inverter controller of any one of Claims 26-29, characterized in that said first memory means comprises read only memory means having information stored in addressable locations therein pertaining to said next address information, said locations addressed by said address information on said address bus, a portion of said address information comprising said binary mode select - signal received from said mode control register means.

Claim 37

Dependent Claim 51 words

The inverter controller of Claim 30 characterized in that said read only memory means comprises a next table ROM and a next line ROM each connected to receive said address information on said address bus for respectively providing two and four bits of next address information to said first register means.

Claim 38

Dependent Claim 74 words

The inverter controller of Claim 31 characterized in that said first register means comprises a table register and a line register each enabled by a third timing signal for respectively receiving said two and four bits of next address information from said next table ROM and said next line ROM, the six bits of output signals from said table and line registers comprising said other portion of said address information on said address bus.

Claim 39

Dependent Claim 54 words

The inverter controller of any one of Claims 26-32 characterized in that said second memory means comprises read only memory means having information stored in addressable locations therein pertaining to the desired firing sequence of said gated conduction-controlled rectifiers in said inverter, said locations being addressed by said address information on said address bus.

Claim 40

Dependent Claim 78 words

The inverter controller of Claim 33 characterized in that said rectifiers in said inverter comprises three pairs of gated conduction-controlled =rectifiers arranged in a bridge configuration for converting a DC input voltage signal into three-phase AC output voltage signals, and in that each of said three pairs of gated conduction-controlled rectifiers has a gated conduction-controlled commutation rectifier associated therewith for turning off its associated rectifier when a commutation pulse is received on the gate of said commutation rectifier.

Claim 41

Dependent Claim 98 words

The inverter controller of Claims 33 or 34 characterized in that said read only memory means comprises first and second next main conduction-controlled rectifiers ROMs, each connected to receive said address " information on said address bus for respectively providing first and second sets of three bit output signal, said first set of three bit output signals representing the next state desired for one rectifier in each of said three pairs of rectifiers, said second set of three bit output signals representing the next state desired for the other rectifier in each of said three pairs of rectifiers.

Claim 42

Dependent Claim 76 words

The inverter controller of Claim 35 characterized in that said second register means comprises first and second main conduction-controlled rectifier registers each enabled by a second timing signal for respectively receiving said first and second sets of three bit output signals from said first and second main conduction-controlled rectifier ROMs, the six bits of output signals from said first and second main conduction- controlled rectifer registers comprising said signals for the controlled rectifiers of said inverter.

Claim 43

Dependent Claim 87 words

The inverter controller of Claims 35 or 36 characterized in that certain of said addressable locations in said read only memory means has information pertaining to permissible times for changing modes of said inverter, said certain addressable locations being addressable by said address information on said address bus to generate a one bit enable mode change signal which is received by said second register means for transmission to said mode control register means upon receipt by said second register means of certain of said second timing signals.

Claim 44

Dependent Claim 56 words

The inverter controller of Claim 36 characterized in that said read only memory means further comprises a next commutate conduction-controlled rectifier ROM connected to receive said address information on said address bus for providing a third set of three bit output signals that represent the next state desired for the six commutation rectifiers of said inverter.

Claim 45

Dependent Claim 36 words

The inverter controller of Claim 38 characterized in that said second register means further comprises a commutation conduction-controlled rectifier register enabled by a fourth timing signal for receiving said third set of three bit output signals.

Claim 46

Dependent Claim 49 words

The inverter controller of Claim 39 characterized in that said commutation conduction-controlled rectifier register comprises a decoder for translating said third set of three bit output signals from said next conduction-controlled rectifier ROM into six gate control signals, one for each of said six commutation rectifiers in said inverter.

Claim 47

Dependent Claim 136 words

The inverter controller of any one of Claims 28-40 characterized in that said means for receiving clock signals and for generating a plurality of timing signals comprises: means for receiving a first clock signal which is six times the desired inverter output frequency and for receiving a second clock signal; counter means for generating a series of address codes in accordance with said second clock signal; memory means having a plurality of addressable locations certain of which contain timing data, said locations addressed by said series of address codes for producing said timing signals each time said certain memory locations are addressed; and timing register means connected to said memory means for producing said timing signals as outputs upon receipt of said second clock signal, wherein one of said timing signals comprises said first timing signals.

Claim 48

Independent Claim 66 words

A method of controlling the firing of solid --state gate controlled rectifying devices in a rectifier bridge that rectifies three-phase AC voltage signals to provide a direct current output, characterized by the step of: providing gate signals to said devices when each phase voltage of said three-phase alternating current voltage signals is most positive and most negative with respect to the other two phase voltage signals.

Claim 49

Independent Claim 66 words

A method of controlling the firing of solid --state gate controlled rectifying devices in a rectifier bridge that rectifies three-phase AC voltage signals to provide a direct current output, characterized by the step of: providing gate signals to said devices when each phase voltage of said three-phase alternating current voltage signals is most positive and most negative with respect to the other two phase voltage signals.

Claim 50

Dependent Claim 62 words

The method of Claim 42, further characterized by the steps of: detecting when the magnitude of each phase voltage of the three-phase alternating current voltage signal input to said rectifier bridge is greater than the other two phase voltages; and correlating the results of said detecting step to determine the most positive and most negative times of each of said phase voltages.

Claim 51

Dependent Claim 154 words

A controller for a rectifier of first, second and third phase alternating current voltage signals for supplying a controlled direct current voltage to a load, said rectifier including three pairs of solid state gate controlled rectifying devices connected in a bridge configuration to a common output bus, each of said pair of devices connected to receive one of said first, second or third phase voltage signals to rectify both the positive half and negative half of the respective applied voltage signal, characterized by: means for detecting when each of said first, second and third voltage signals is greater than the other two signals and for providing output signals thereupon; and means responsive to said output signals for providing gate control signals to turn on the gates of said solid state gate controlled rectifying devices when each of said voltage signals are most positive and most negative with respect to the other two voltage signals.

Claim 52

Dependent Claim 154 words

A controller for a rectifier of first, second and third phase alternating current voltage signals for supplying a controlled direct current voltage to a load, said rectifier including three pairs of solid state gate controlled rectifying devices connected in a bridge configuration to a common output bus, each of said pair of devices connected to receive one of said first, second or third phase voltage signals to rectify both the positive half and negative half of the respective applied voltage signal, characterized by: means for detecting when each of said first, second and third voltage signals is greater than the other two signals and for providing output signals thereupon; and means responsive to said output signals for providing gate control signals to turn on the gates of said solid state gate controlled rectifying devices when each of said voltage signals are most positive and most negative with respect to the other two voltage signals.

Claim 53

Dependent Claim 159 words

The rectifier controller of Claim 44 characterized in that said detection means comprises voltage detection means for receiving said first, second and third voltage signals and for providing six outputs when respective ones of said voltage signals are greater than the others; and in that said means for providing gate control signals comprises logic means responsive to said six outputs for providing a first set of three gate control signals for indicating which of said voltage signals are most positive at 1 any point in time, and for providing a second set of three gate control signals for indicating which of said voltage signals are most negative at any point in time, said first set of three gate control signals connected to be applied to the gates of one of said devices in each pair, said second set of three gate control signals connected to be applied to the gates of the other of said devices in each pair.

Claim 54

Dependent Claim 38 words

The rectifier controller of Claim 45 characterized in that said logic means is further responsive to comparator means also responsive to said voltage signals for generating a dwell output each time any of said voltage signals are equal.

Claim 55

Dependent Claim 37 words

The rectifier controller of Claim 46 further characterized by: means connected to said logic means and responsive to an input command for delaying said first and second sets of gate control signals for a predetermined time period.

Claim 56

Dependent Claim 86 words

The rectifier controller of Claim 47 characterized in that said means responsive to an input command comprises: means for receiving said input command; counter means connected to said means for receiving said input command for counting a number in accordance with said input command and for providing a count output signal when said number has been counted; and means connecting said,count output signal to said logic means to delay said gate control signals in time in accordance with the time period required to count said number.

Claim 57

Independent Claim 58 words

A method for fault detection for an inverter having a plurality of conduction-controlled solid state devices supplied by a source of direct current on a DC bus, characterized by the steps of: (a) detecting a shoot-through condition in said conduction-controlled solid state devices (b) short circuiting said DC bus in response to the detection of said shoot-through condition

Claim 58

Independent Claim 58 words

A method for fault detection for an inverter having a plurality of conduction-controlled solid state devices supplied by a source of direct current on a DC bus, characterized by the steps of: (a) detecting a shoot-through condition in said conduction-controlled solid state devices (b) short circuiting said DC bus in response to the detection of said shoot-through condition

Claim 59

Dependent Claim 61 words

A fault detector for an inverter having a plurality of conduction-controlled solid state devices supplied by a source of direct current on a DC bus, characterized by: means for detecting a shoot-through condition which exists in said conduction-controlled solid state devices of said inverter; and means responsive to said means for detecting a shoot-through condition for short circuiting said DC bus.

Claim 60

Dependent Claim 61 words

A fault detector for an inverter having a plurality of conduction-controlled solid state devices supplied by a source of direct current on a DC bus, characterized by: means for detecting a shoot-through condition which exists in said conduction-controlled solid state devices of said inverter; and means responsive to said means for detecting a shoot-through condition for short circuiting said DC bus.

Claim 61

Dependent Claim 53 words

The fault detector of Claim 50 characterized in that said means for detecting a shoot-through condition comprises: capacitor means connected across said DC bus; inductor means connected in series with said DC bus; and means responsive to the current from said. capacitor means for generating a shoot-through voltage which indicates a shoot-through condition.

Claim 62

Dependent Claim 34 words

The fault detector of Claim 51 characterized in that said means responsive ito the current from said capacitor means comprises a transformer having a primary coil for receiving said current and a secondary coil.

Claim 63

Dependent Claim 28 words

The fault detector of Claim 52 further characterized by means for blocking the output voltage of said transformer until a predetermined voltage is present across said secondary coil.

Claim 64

Dependent Claim 33 words

The fault detector of Claim 53 characterized in that said means for blocking the output voltage of said transformer comprises a Zener diode in series connection with said secondary coil of said transformer.

Claim 65

Dependent Claim 30 words

The fault detector of any one of Claims 50-54 characterized in that said means for short circuiting said DC bus comprises a condution controlled rectifier connected across said DC bus.

Claim 66

Dependent Claim 16 words

The fault detector of Claims 52-55 characterized in that said transformer comprises a saturable core transformer.

Method and apparatus for controlling power distribution of an electric utility

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