EP0021776A1
Expired / Lapsed
EP
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Semiconductor memory device and method of making same
Assignee: Fujitsu Ltd
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Filing: 1980-06-17
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Granted: —
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Expires: 2000-06-17
Abstract
Abstract A semiconductor memory device includes a plurality of memory cells formed on a semiconductor substrate (10) of one conductivity type, each of the memory cells comprising a first region (16) formed on the semiconductor substrate (1); a gate-oxide layer (18) formed on the first region (16); a window (38) through the gate-oxide layer (18) for diffusing impurities through; a gate electrode (20) formed on the gate-oxide layer (18); a second region (31) of opposite conductivity type to the first region (16) formed under the window (38), by diffusing impurities through the window (38), into the first region (16), the second region (31) extending under a part of the gate electrode (20); and, a third region (14) having the same conductivity type as the first region (16), formed on the second region (31) and underthe window (38), by diffusing impurities through the window (38) into the second region (31), the gate electrode (20) covering the surface of the first region (16) and the second region (31) through the gate-oxide layer (18). This construction enables the size of the individual memory cells to be reduced to substantiall y4F 2 , where F is equal to the minimum width of a patterning line. This is approximately half the minimum size previously achieved.
Inventors
- 👤 Junji Sakurai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 04:03
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
145 words
A semiconductor memory device including a plurality of memory cells formed on a semiconductor substrate of one conductivity type, each of the memory cells comprising a first region formed on the semiconductor substrate; a gate-oxide layer formed on the first region; a window through the gate-oxide layer for diffusing impurities through; a gate electrode formed on the gate-oxide layer; a second region of opposite condudivity type to the first region formed under the window, by diffusing impurities through the window into the first region, the second region extending under a part of the gate electrode; and, a third region having the same conductivity type as the first region, formed on the second region and under the window, by diffusing impurities through the window into the second region, the gate electrode covering the surface of the first region and the second region through the gate-oxide layer.
Claim 2
Dependent Claim
145 words
A semiconductor memory device including a plurality of memory cells formed on a semiconductor substrate of one conductivity type, each of the memory cells comprising a first region formed on the semiconductor substrate; a gate-oxide layer formed on the first region; a window through the gate-oxide layer for diffusing impurities through; a gate electrode formed on the gate-oxide layer; a second region of opposite condudivity type to the first region formed under the window, by diffusing impurities through the window into the first region, the second region extending under a part of the gate electrode; and, a third region having the same conductivity type as the first region, formed on the second region and under the window, by diffusing impurities through the window into the second region, the gate electrode covering the surface of the first region and the second region through the gate-oxide layer.
Claim 3
Dependent Claim
35 words
A semiconductor memory device according to claim 1, wherein the size of the individual memory cells is substantially equal to 4F 2 , where F is equal to the minimum width of a patterning line.
Claim 4
Dependent Claim
61 words
A semiconductor memory device according to claim 1 or 2, in which each of the memory cells includes one MOS transistor and wherein a channel region of the transistor is formed under the gate-oxide layer and between the first region and the third region, the first region and the third region forming source and drain regions respectively of the MOS transistor.
Claim 5
Dependent Claim
22 words
A semiconductor memory device according to any one of the preceding claims, wherein the second region is formed on the first region.
Claim 6
Dependent Claim
30 words
A semiconductor memory device according to any one of the preceding claims, wherein the first region is an impurity diffusion region formed by the diffusion of impurities through the window.
Claim 7
Dependent Claim
46 words
A semiconductor memory device according to any one of the preceding claims, in which each memory cell also includes a capacitor formed by the junction capacitance between the first region and the second region as well as that between the first region and the semiconductor substrate.
Claim 8
Dependent Claim
32 words
A semiconductor memory device according to any one of the preceding claims, wherein two adjacent memory cells are symmetrical and wherein the third region is common to the two adjacent memory cells.
Claim 9
Dependent Claim
22 words
A semiconductor memory device according to any one of claims I to 5, wherein each memory cell is of the charge-pumping type.
Claim 10
Dependent Claim
27 words
A semiconductor memory device according to any one of claims I to 5, wherein the windows of predetermined of the memory cells are covered by insulating films.
Claim 11
Dependent Claim
21 words
A semiconductor memory device according to any one of the preceding claims, in which the memory device is a read-only memory.
Claim 12
Independent Claim
151 words
A method of making a semiconductor memory device including a plurality of memory cells, comprising forming a first region on a semiconductor substrate, forming a gate-oxide layer on the first region, forming a window through the gate oxide layer for diffusing impurities through, the window having its dimensions equal to the minimum width of a patterning line, forming a gate electrode on the gate-oxide layer; forming a second region of opposite conductivity type to the first region under the window, by diffusing impurities through the window into the first region, the second region extending under a part of the gate electrode; and, forming a third region having the same condutivity type as the first region, on the second region and under the window, by diffusing impurities through the window into the second region, the gate electrode covering the surface of the first region and the second region through the gate-oxide layer.
Claim 13
Independent Claim
151 words
A method of making a semiconductor memory device including a plurality of memory cells, comprising forming a first region on a semiconductor substrate, forming a gate-oxide layer on the first region, forming a window through the gate oxide layer for diffusing impurities through, the window having its dimensions equal to the minimum width of a patterning line, forming a gate electrode on the gate-oxide layer; forming a second region of opposite conductivity type to the first region under the window, by diffusing impurities through the window into the first region, the second region extending under a part of the gate electrode; and, forming a third region having the same condutivity type as the first region, on the second region and under the window, by diffusing impurities through the window into the second region, the gate electrode covering the surface of the first region and the second region through the gate-oxide layer.
References Cited (Backward Citations)
DE1906324A1
Cited
US3694704A
Cited
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