EP0021133A2
Expired / Lapsed
EP
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Semiconductor device comprising an interconnection electrode and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1980-06-02
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Granted: —
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Expires: 2000-06-02
Abstract
Abstract A method for manufacturing a semiconductor device having a high breakdown voltage and a high reliability, comprises (a) forming on a semiconductor substrate (12) an insulating layer (13) having a diffusion window (14); (b) forming an impurity-doped poly-silicon layer (15) on the insulating layer (13) and on that portion of the semiconductor substrate (2) which is exposed through the diffusion window (14); (c) forming an undoped poly-silicon layer (16) on the impurity-doped poly-silicon layer (15); (d) thermally oxidizing the substrate (2) with the insulating layer (13), impurity-doped poly-silicon layer (15) and undoped poly-silicon layer (16), thus diffusing the impurity from the impurity-doped poly-silicon layer (15) into the semiconductor substrate (12) through the diffusion window (14) and converting the undoped poly-silicon layer (16) to a silicon oxide layer (18); (e) forming on the silicon oxide layer (18) an oxidation-resisting mask layer (19) in a desired pattern; and (f) thermally oxidizing the substrate (12) with the insulating layer (13), impurity-doped poly-silicon layer (15), silicon oxide layer (18) and mask layer (19), thus converting those portions of the impurity-doped poly-silicon layer (15) which lie beneath those portions of the silicon oxide (18) layer which are exposed through the mask layer (19) to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer (21) having a desired pattern.
Inventors
- 👤 Jiro Oshima
- 👤 Masaharu Aoyama
- 👤 Seiji Yasuda
- 👤 Toshio Yonezawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 07:43
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; H10D; H10D64/00; H10D64/01; H10D64/011; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P95/00; H10W20/42; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/92
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
184 words
A method for manufacturing a semiconductor device comprising: (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b). forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.
Claim 2
Independent Claim
184 words
A method for manufacturing a semiconductor device comprising: (a) forming on a semiconductor substrate an insulating layer having a diffusion window; (b). forming an impurity-doped poly-silicon layer on the insulating layer and on that portion of the semiconductor substrate which is exposed through the diffusion window; (c) forming an undoped poly-silicon layer on the impurity-doped poly-silicon layer; (d) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer and undoped poly-silicon layer, thus diffusing the impurity from the impurity-doped poly-silicon layer into the semiconductor substrate through the diffusion window and converting the undoped poly-silicon layer to a silicon oxide layer; (e) forming on the silicon oxide layer an oxidation-resisting mask layer in a desired pattern; and (f) thermally oxidizing the substrate with the insulating layer, impurity-doped poly-silicon layer, silicon oxide layer and mask layer, thus converting those portions of the impurity-doped poly-silicon layer which lie beneath those portions of the silicon oxide layer which are exposed through the mask layer to impurity-doped silicon oxide layers, whereby the remaining portions of the impurity-doped poly-silicon layer provide an interconnection electrode layer having a desired pattern.
Claim 3
Dependent Claim
11 words
A method according to claim 1, wherein said impurity is arsenic.
Claim 4
Dependent Claim
17 words
A method according to claim 1, wherein said undoped poly-silicon layer is 500 to 1,000 A thick.
Claim 5
Dependent Claim
49 words
A method according to claim 1 or 2, wherein the impurity concentration of said undoped silicon oxide layer is 1 x 10 17 cm- 3 and that of said impurity-doped silicon oxide layer is 1 x 10 18 cm- 3 to 1 x 1 0 2 2 c m-3.
Claim 6
Dependent Claim
36 words
A method according to claim 1 or 2, wherein said impurity-doped poly-silicon layer is formed by method selected from the group consisting of chemical vapor deposition, sputtering and impurity ion implantation to an undoped poly-silicon layer.
Claim 7
Dependent Claim
16 words
A method according to claim 1, wherein said oxidation-resisting mask layer is made of silicon nitride.
Claim 8
Dependent Claim
42 words
A method according to claim 1, further comprising steps of removing said oxidation-resisting mask layer, forming a contact hole in the silicon oxide layer laid on said interconnection electrode layer, and forming a metal electrode in a region including said contact hole.
Claim 9
Dependent Claim
142 words
A semiconductor device comprising: (a) a semiconductor substrate having an impurity-doped region; (b) an insulating layer covering the surface of the semiconductor substrate except for the surface of the impurity-doped region; (c) an interconnection electrode layer formed on selected portions of the insulating layer and on the impurity-doped region, said interconnection electrode layer being made of poly-silicon doped with the same impurity as that of the impurity-doped region; (d) a first undoped silicon oxide layer formed on the interconnection electrode layer, and (e) a second silicon oxide layer consisting of an upper undoped portion and a lower doped portion which covers those portions of the insulating layer which are not covered with the interconnection electrode layer and which lie respectively along the interconnection electrode layer and the first undoped silicon oxide layer, thereby defining the region occupied by the interconnection electrode layer.
Claim 10
Dependent Claim
142 words
A semiconductor device comprising: (a) a semiconductor substrate having an impurity-doped region; (b) an insulating layer covering the surface of the semiconductor substrate except for the surface of the impurity-doped region; (c) an interconnection electrode layer formed on selected portions of the insulating layer and on the impurity-doped region, said interconnection electrode layer being made of poly-silicon doped with the same impurity as that of the impurity-doped region; (d) a first undoped silicon oxide layer formed on the interconnection electrode layer, and (e) a second silicon oxide layer consisting of an upper undoped portion and a lower doped portion which covers those portions of the insulating layer which are not covered with the interconnection electrode layer and which lie respectively along the interconnection electrode layer and the first undoped silicon oxide layer, thereby defining the region occupied by the interconnection electrode layer.
Claim 11
Dependent Claim
12 words
A semiconductor device according to claim 8, wherein said impurity is arsenic.
Claim 12
Dependent Claim
69 words
A semiconductor device according to claim 8 or 9, wherein said first silicon oxide layer and the upper undoped portion of said second silicon oxide layer have an impurity concentration of 1 x 10 17 cm- 3 or less, and the lower doped portion of said second silicon oxide layer has an impurity concentration of 1 x 10 18 cm- 3 to 1 x 10 22 c m-3 .
Claim 13
Dependent Claim
17 words
A semiconductor device according to any one of claims 8 to 10, which is a bipolar transistor.
References Cited (Backward Citations)
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