EP0018754A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Speed independent selector switch for digital communication networks
Assignee: Unisys Corp
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Filing: 1980-04-18
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Granted: —
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Expires: 2000-04-18
Abstract
Abstract A speed independent selection switch designed for pipelined message transmission through digital communication networks. The selector routes a message from the input path to one of two output paths selected by the first bit of the message, that bit then being discarded.
Inventors
- 👤 Becky J. Clark
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 19:54
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/25; G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375; G06F15/17381; G06F15/76; G06F15/80; H04L49/10; H04L49/103; H04L49/15; H04L49/1515; H04L49/1546; H04L49/40
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
78 words
A selection switch for receiving signals from a node of a digital communication network and transmitting those signals to one of two other nodes, said switch comprising: a pair of switch circuits, each adapted to receive a set of said data signals; and an address circuit to receive said data signals preceded by an address signal specifying which of two nodes is to be selected for subsequent transmission and to signal the corresponding one of said switch circuits.
Claim 2
Dependent Claim
78 words
A selection switch for receiving signals from a node of a digital communication network and transmitting those signals to one of two other nodes, said switch comprising: a pair of switch circuits, each adapted to receive a set of said data signals; and an address circuit to receive said data signals preceded by an address signal specifying which of two nodes is to be selected for subsequent transmission and to signal the corresponding one of said switch circuits.
Claim 3
Dependent Claim
38 words
A selector switch according to Claim 1 further including: a pair of end of message circuits, one for each of said switch circuits to receive an end of message signal subsequent to the receipt of a data signal.
Claim 4
Dependent Claim
34 words
A selection switch according to Claim 2 further including: a clear circuit adapted to receive an acknowledge end of message signal from the selected node and to transmit that signal to the original node.
Claim 5
Dependent Claim
32 words
A selection switch according to Claim 3, wherein: said address circuit includes means to remove the first address bit of the address upon selection of one of the pair of switch circuits.
Claim 6
Dependent Claim
102 words
A selection switch for receiving signals from a node of a digital communication network and transmitting those signals to one of two other nodes, said switch comprising: a pair of switch circuits, each adapted to receive a set of said data signals; an address circuit to receive said data signals preceded by an address signal specifying which of two nodes is to be selected for subsequent transmission and to signal the corresponding one of said switch circuits; and said address circuit includes means to remove the first address bit of the address upon selection of one of the pair of switch circuits.
Claim 7
Dependent Claim
102 words
A selection switch for receiving signals from a node of a digital communication network and transmitting those signals to one of two other nodes, said switch comprising: a pair of switch circuits, each adapted to receive a set of said data signals; an address circuit to receive said data signals preceded by an address signal specifying which of two nodes is to be selected for subsequent transmission and to signal the corresponding one of said switch circuits; and said address circuit includes means to remove the first address bit of the address upon selection of one of the pair of switch circuits.
Claim 8
Dependent Claim
68 words
A selection switch according to Claim 5 further including: a plurality of buffer circuits each connected to one of said switch circuits each of said buffer circuits including a two cell queue to receive a data bit from the switch means in the first cell and transfer that bit to the second cell only when the second cell is empty, such buffer circuit enabling pipelining through connected switches.
Claim 9
Dependent Claim
38 words
A selector switch according to Claim 5 further including: a pair of end of message circuits, one for each of said switch circuits to receive an end of message signal subsequent to the receipt of a data signal.
Claim 10
Dependent Claim
34 words
A selection switch according to Claim 7 further including: a clear circuit adapted to receive an acknowledge end of message signal from the selected node and to transmit that signal to the original node.
References Cited (Backward Citations)
US3962706A
Cited
US4153932A
Cited
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