Method and device for speech signal reconstruction in packet switched telecommunication networks

Claim 2

Method for the correct reconstruction of the speech signal at a receiving node of a packet switched communication network, a transmitting node of which emits packets built up from digitized samples of said signal, relevant to the active s.agnal periods (taikspurts),received with a random delay varying according to the packet, the receiving operations being controlled by a clock that is independent of the transmission clock and is started upon the reception at the receiving node of a packet concerning a call characterized in that the delay suffered by the first packet of each talkspurt is estimated, the estimate being progressively made to converge to the actual value by a progressive synchronization of the receiving and . transmitting clocks, and in that this packet is temporarily stored, before its introduction into the output queue of the receiving node, for a time (TA - t α ) dependent on said estimated delay (t α ) and such that the overall delay suffered by said packet is not lower than a predetermined minimum delay (Tλ) that reduces to a minimum the variance of said random delay.

Claim 3

Method according to claim 1, characterized in that said synchronization is' effected by determining the minimum possible value (t χ ) for the arrival instant of each packet, on the basis of the time taken to build up all the preceding packets, of the birth time (t ) of the first packet .of a talkspurt and of the deterministic service time (Td) of the network, by comparing said minimum value (t χ ) with value (t r ) indicated by the receiving clock (OP) and advancing said receiving clock (OP) to said minimum value (t χ ) in case this one is higher than the value (t ) indicated by the receiving clock (OP).

Claim 4

Device associated to a receiving node of a packet-switched communication network for realizing the process according to claim 1, characterized in that it comprises the following units: - a buffer memory (M6) temporarily storing the packets received and introducing for the first packet of each talkspurt the possible additional delay; - a bank of five memory devices (MI, M2, M3, M4, M5) storing for every packet, respectively: the serial number decreased by a unit (k- 1); the time taken to form a packet (Ts); the value of the minimum delay (T λ ) that the first packet of each talkspurt must suffer;the overall service time (Td); the birth time (t, of the first packet of a talkspurt; - a further memory (M7) connected to the first memory (Ml) of said bank and storing the contents thereof whenever said first memory is updated; - a first comparator (Cl) having one input connected tothe first memory (MEl) of said bank and a second input connected to a comparison threshold fixed and equal to 0, said comparator comparing the contents of said memory (MEl) with said threshold, and signalling whether or not the processed packet is the first of a talkspurt; - a multiplying register (RM), connected with the first and second memories (ME1, ME2) of said bank, and computing the time (k - 1)·Ts elapsed between the transmission of the first packet of a talkspurt and the transmission of the packet that is being processed; - a programmable clock (OP), that indicates the time starting from the instant of the first reception of a packet relevant to a conversation and that, at the arrival of a packet,is advanced towards a minimum value (t χ ) possible for the instant the arrival of such packet until value (t ) is higher than or equal to said minimum value (t α ); - an adding register (RS) that is connected with said multiplying register (RM), said programmable clock (OP) and the third, fourth, fifth memories (ME3, ME4, ME5) of said bank, in order to compute said minimum value (t x ) possible for the instant of arrival, to estimate the delay (t ) suffered by the first packet of a talkspurt and to determine, on the basis of said delay, the possible additional delay (Tλ - t d ) said packet is to suffer; - a second comparator (C2) with two inputs, able either to signal that two values present on said inputs are equal, or to signal which value is higher, in case of inequality, said inputs being connectable in turns to the first memory of said bank (Ml) and to said further memory (M7) to recognize the arrival of a new packet, or to said adding register (RS) and to said programmable clock OP to compare the time (t γ ) indicated by the clock (OP) with said minimum value (t x ) possible for the arrival instant of a packet, or yet to the third memory of said bank (M3) and to said adding register (RS), to determine whether the estimated delay (t d ) for the packet of a talkspurt is still inferior to the minimum delay to be introduced (Tλ). - a first gate (PI) able to establish the connection between said buffer memory (M6) and the node processor; - six further gates (P2 ... P7) able to establish the connections between the various units of the device; - a sequential logic network (LS) programmed so as to control the opening of said gates on the basis of information it receives from the first and second comparator (Cl, C2) and the adding register (RS).

Claim 5

Method and device for the reconstruction of speech signal in a packet switched communication network, basically as described in the text and depicted in the annexed drawings.

Claim 6

Method and device for the reconstruction of speech signal in a packet switched communication network, basically as described in the text and depicted in the annexed drawings.