EP0015554A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Comparator circuit
Assignee: NEC Corp
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Filing: 1980-03-06
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Granted: —
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Expires: 2000-03-06
Abstract
Abstract A comparator circuit comprises a differential amplifier (1) having a pair of inputs (2', 3') and a switch circuit (21) arranged between the pair of inputs (2', 3'), wherein the switch circuit (21) is made conductive state prior to the comparison operation to delete potential difference between the pair of inputs (2', 3'). The comparator circuit which can be easily realized in the form of an integrated circuit device can achieve a high speed operation even for signals fed from a high impedance signal source to the stray capacitance found at the comparator input. The comparator circuit is suitably applied to an AD/converter circuit especially of sequential comparison type.
Inventors
- 👤 Kyuichiuc/Ounec Corporation Hareyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:28
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/249; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
75 words
A comparator circuit comprising a differential amplifier circuit having a pair or input terminals, said pair of input terminals receiving signals to be compared, switching circuit arranged between said pair of input terminals, and a control means for making said switch circuit conductive state prior to comparison operation to delete difference in potential between said pair of input terminals, wherein comparison result of said signals is enabled when said switch circuit is in non-cinductive state.
Claim 2
Dependent Claim
75 words
A comparator circuit comprising a differential amplifier circuit having a pair or input terminals, said pair of input terminals receiving signals to be compared, switching circuit arranged between said pair of input terminals, and a control means for making said switch circuit conductive state prior to comparison operation to delete difference in potential between said pair of input terminals, wherein comparison result of said signals is enabled when said switch circuit is in non-cinductive state.
Claim 3
Dependent Claim
16 words
The circuit according to claim 1, further comprising a latch circuit for storing said comparison result.
Claim 4
Dependent Claim
22 words
The circuit according to claim 2, wherein said control means includes means for supplying said switch circuit with a first clock signal.
Claim 5
Dependent Claim
36 words
The circuit according to claim 3, further comprising means for providing said latch circuit with a second clock signal as write control signal, phase of said second clock signal being different from said first clock signal.
Claim 6
Dependent Claim
25 words
The circuit according to claim 3, wherein said switch circuit includes an N-channel field effect transistor and a P-channel field effect transistor connected in parallel.
Claim 7
Dependent Claim
54 words
A comparator circuit comprising a differential amplifier circuit, switching means coupled between differential input terminals of said differential amplifier circuit, and means for controlling opened and closed states of said switching means, said differential input terminals receiving inputs to be compared, and the output of said differential amplifier circuit serving as a comparator output.
Claim 8
Dependent Claim
54 words
A comparator circuit comprising a differential amplifier circuit, switching means coupled between differential input terminals of said differential amplifier circuit, and means for controlling opened and closed states of said switching means, said differential input terminals receiving inputs to be compared, and the output of said differential amplifier circuit serving as a comparator output.
Claim 9
Dependent Claim
23 words
A comparator circuit as claimed in Claim 6, which further comprises a flip-flop circuit for writing the output of said differential amplifier circuit.
Claim 10
Dependent Claim
92 words
A circuit comprising first means for receiving an analog signal, second means for producing a plurality of weighted reference signals, third means for selectively combining said reference signals to produce a combined signal, fourth means for detecting difference between said analog signal and said combined signal, differential amplifier having an input terminal supplied with a potential having a value corresponding to the detected difference, fifth means for operatively clamping said input terminal at a fixed potential and control means responsive to an output of said differential amplifier for controlling said third means.
Claim 11
Dependent Claim
92 words
A circuit comprising first means for receiving an analog signal, second means for producing a plurality of weighted reference signals, third means for selectively combining said reference signals to produce a combined signal, fourth means for detecting difference between said analog signal and said combined signal, differential amplifier having an input terminal supplied with a potential having a value corresponding to the detected difference, fifth means for operatively clamping said input terminal at a fixed potential and control means responsive to an output of said differential amplifier for controlling said third means.
Claim 12
Dependent Claim
22 words
The circuit according to claim 9, wherein said fifth means includes a switch having a control terminal supplied with a timing signal.
Claim 13
Dependent Claim
15 words
The circuit according to claim 9, wherein said second means includes a resistor ladder circuit.
Claim 14
Dependent Claim
113 words
An analog to digital converter circuit comprising a voltage to current, converter circuit for converting an analog voltage to an analog current, a resistor ladder circuit producing a plurality of weighted currents, a current summing line, a current feed circuit for selectively supplying said current summing line with a combination of currents, a detection circuit for detecting difference in value between said analog current and a current at said current summing line, an differential amplifier having a first terminal biased at a predetermined potential and a second terminal supplied with a potential having a value corresponding to the detected difference, and a switch circuit arranged between said first terminal and said second terminal.
Claim 15
Dependent Claim
113 words
An analog to digital converter circuit comprising a voltage to current, converter circuit for converting an analog voltage to an analog current, a resistor ladder circuit producing a plurality of weighted currents, a current summing line, a current feed circuit for selectively supplying said current summing line with a combination of currents, a detection circuit for detecting difference in value between said analog current and a current at said current summing line, an differential amplifier having a first terminal biased at a predetermined potential and a second terminal supplied with a potential having a value corresponding to the detected difference, and a switch circuit arranged between said first terminal and said second terminal.
Claim 16
Dependent Claim
59 words
The circuit according to claim 11, further comprising a plurality of latch circuits, a shift resister, a gate circuit for feeding said latch circuits with outputs of said shift register, a start control circuit responsive to start command signal for producing a train of control signals, and a circuit connection for applying said control signals to said switch circuit.
References Cited (Backward Citations)
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