EP0009367A1
Expired / Lapsed
EP
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Gate turn-off thyristor
Assignee: Hitachi Ltd
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Filing: 1979-09-12
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Granted: —
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Expires: 1999-09-12
Abstract
Abstract A gate turn-off thyristor of a short-circuited emitter configuration comprises a semiconductor substrate (1) of a P E -N B -P B -N E four-layer structure, wherein a P E -layer (2) is short-circuited through a N B -layer (3 and 4) and an anode (8). The N B -layer includes heavily doped regions (3) with which the anode is in ohmic contact with low resistance. The P E -layer (2) is at least partly at the area corresponding to the projection of the N E -layer (6) onto the surface contacted by the anode (8). The thickness of the heavily doped regions (3) is greater than of the P E -layer (2). This structure achieves satisfactory gate turn-off characteristics, although the semiconductor substrate is not doped with a life time killer impurity.
Inventors
- 👤 Takahiro Nagano
- 👤 Isamu Sanpei
- 👤 Shuroku Sakurada
- 👤 Masaru Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 17:16
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/01; H10D18/60; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
231 words
A gate turn-off thyristor comprising a semiconductor substrate (1) which has opposite major surfaces, and contains four semiconductor layers (2,3 and 4,5,6) which constitute two inner layers (3 and 4,5) and two outer layers (2,6) and adjacent pairs of which are of opposite conductivity type, there being an anode (8) in ohmic contact with one of the outer layers (2), or cathode (9) in ohmic contact with the other of the outer layers (6) and a gate electrode in contact with one of the inner layers (5), characterized in that: the inner layer (3 and 4) adjacent the outer layer (2) contacted by the anode (8) has a region of low impurity concentration (4) and at least one region of high impurity concentration (3), the latter being exposed both at a boundary with the outer layer (2) and at the major surface contacted by the anode (8), the said outer layer (2) having a lesser thickness (in the direction transverse to the major surfaces) than said high impurity concentration region (3) and being exposed at the major surface contacted by the anode (8) at an area which at least partially corresponds to the projection onto that major surface of the area of the other outer layer (6) exposed at the other major surface, the anode (8) being in contact with both said outer layer (2) and the high impurity concentration region.
Claim 2
Dependent Claim
231 words
A gate turn-off thyristor comprising a semiconductor substrate (1) which has opposite major surfaces, and contains four semiconductor layers (2,3 and 4,5,6) which constitute two inner layers (3 and 4,5) and two outer layers (2,6) and adjacent pairs of which are of opposite conductivity type, there being an anode (8) in ohmic contact with one of the outer layers (2), or cathode (9) in ohmic contact with the other of the outer layers (6) and a gate electrode in contact with one of the inner layers (5), characterized in that: the inner layer (3 and 4) adjacent the outer layer (2) contacted by the anode (8) has a region of low impurity concentration (4) and at least one region of high impurity concentration (3), the latter being exposed both at a boundary with the outer layer (2) and at the major surface contacted by the anode (8), the said outer layer (2) having a lesser thickness (in the direction transverse to the major surfaces) than said high impurity concentration region (3) and being exposed at the major surface contacted by the anode (8) at an area which at least partially corresponds to the projection onto that major surface of the area of the other outer layer (6) exposed at the other major surface, the anode (8) being in contact with both said outer layer (2) and the high impurity concentration region.
Claim 3
Dependent Claim
21 words
A thyristor according to claim 1, wherein each of said outer layers (2,6) is divided into a plurality of semiconductor regions.
Claim 4
Dependent Claim
61 words
A thyristor according to claim 2, wherein the regions of the outer layer (2) contacted by the anode are interconnected by semiconductor regions (21) of the same conductivity type as that of the outer layer (2) at locations outside the areas corresponding to the projections of said regions of the outer layer (6) onto the major surface contacted by the anode.
Claim 5
Dependent Claim
29 words
A thyristor according to claim 3 wherein the anode (8) additionally contacts the said semiconductor regions (21) interconnecting said regions of the outer layer (2) contacted by the anode.
Claim 6
Dependent Claim
64 words
A thyristor according to claim 2 wherein the regions of the outer layer (6) contacted by the cathode are interconnected by semiconductor regions of the same conductivity type as that of said outer layer (6) at locations outside the areas corresponding to the projections of said regions of the outer layer (2) contacted by the anode onto the major surface contacted by the cathode.
Claim 7
Dependent Claim
28 words
A thyristor according to claim 5, wherein the cathode (9) additionally contacts the said semiconductor regions interconnecting said regions of the outer layer (6) contacted by the anode.
Claim 8
Dependent Claim
28 words
A thyristor according to any one of the preceding claims wherein said high impurity concentration regions (3) is exposed at a side wall portion of said semiconductor substrate.
Claim 9
Dependent Claim
46 words
A thyristor according to any one of the preceding claims whereinfue outer layer (2) contacted by the anode and the inner layer (5) contacted by the gate electrode are of P type conductivity, while the other two layers (3 and 4,6) are of N type conductivity.
Claim 10
Dependent Claim
47 words
A thyristor according to any one of claims 1 to 3 wherein the outer layer (2) contacted by the anode and the inner layer (5) contacted by the gate electrode are of N-type conductivity, while the other two layers (3 and 4,6) are of P conductivity type.
References Cited (Backward Citations)
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