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DE3841602A1 Expired / Lapsed DE ⏱️ 0.0 years remaining

VIRTUAL MACHINE SYSTEM

Assignee: Hitachi Ltd
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Filing: 1988-12-09
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Granted: —
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Expires: 2008-12-09
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Abstract

Abstract A virtual machine system, which has a two-stage address translation mechanism, for processing a high-speed address translation in several virtual machines. The way in which the address translation to be processed is made possible is that address constants, which are held in a holding device (8) and contain "zero", are added to the output of a first address translation (2), that a second address translation (9) is carried out, and that an output of the first address translation (2), to which the address constants have been added, or an output of the second address translation (9) is selected (14). The address translation for the several different areas is carried out by switching a value for the address constants which are held in the holding device (8). <IMAGE>

Inventors

  • 👤 Toru Ohtsuki

Bibliographic Details

Application Number —
Jurisdiction DE
Data Source google_patents
Last Synchronized 2026-11-09 04:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843; G06F12/00; G06F12/02; G06F12/0223; G06F12/0292

Claims Analysis

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References Cited (Backward Citations)

US4285040A Cited

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