CA1277426C
Expired / Lapsed
CA
⏱️ 0.0 years remaining
Multiprocessor data processing system
Assignee: EMC Corp
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Filing: 1986-11-13
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Granted: 1990-12-04
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Expires: 2006-11-13
Abstract
Abstract ABSTRACT OF THE DISCLOSURE A multiple processor system in which a plurality of co-equal processors share a common memory which includes a data structure for storing machine state information for a plurality of processing tasks (jobs). The instruction set of each of the processor includes a job processor instruction for storing in the data structure the current of the machine state information of a processing task being executed by a processor at the time such execution has been stopped either because of an interruption thereof or because an allotted time period assigned to a processor for executing that task is over. The processor can then select another processing task and issue another instruction (JP LOAD) to obtain the machine state information therefor from the data structure to permit such other task to be executed using such machine state information. A further instruction for permitting a faster load operation can also be issued by a processor when only a portion of the machine state information is required to be loaded. Other instructions are provided for various purposes useful in the multiple processor context.
Inventors
- 👤 Daniel R. Kerns
- 👤 John F. Pilat
- 👤 Dana A. Kirkpatrick
- 👤 John R. Gilgis
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-10-31 16:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4831; G06F9/4837; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/30076; G06F9/3009; G06F9/38; G06F9/3836; G06F9/3851; G06F9/461; G06F9/463
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
161 words
A multiple processor data processing system comprising: a plurality of co-equal processors; a common memory the use of which is shared by said plurality of processors, a portion of said memory being a data structure having a plurality of state block portions for storing machine state information associated with a plurality of processing tasks, each of said portions corresponding to one of said plurality of processing tasks; each of said processors being capable of executing a set of instructions and having operating systems for issuing instructions of said instruction set, said instruction set including a job processor flush instruction; each processor being responsive to the issuance of said job processor flush instruction, when the execution of a current processing task by said processor is stopped, for storing into the state block portion of said data structure corresponding to the processing task which is being stopped the current internal machine state information of said processor at the time said execution was stopped.
Claim 2
Dependent Claim
161 words
A multiple processor data processing system comprising: a plurality of co-equal processors; a common memory the use of which is shared by said plurality of processors, a portion of said memory being a data structure having a plurality of state block portions for storing machine state information associated with a plurality of processing tasks, each of said portions corresponding to one of said plurality of processing tasks; each of said processors being capable of executing a set of instructions and having operating systems for issuing instructions of said instruction set, said instruction set including a job processor flush instruction; each processor being responsive to the issuance of said job processor flush instruction, when the execution of a current processing task by said processor is stopped, for storing into the state block portion of said data structure corresponding to the processing task which is being stopped the current internal machine state information of said processor at the time said execution was stopped.
Claim 3
Dependent Claim
35 words
A system in accordance with claim 1 wherein the internal machine state of a processor which has responded to said job processor flush instruction is retained in said processor during the execution of said instruction.
Claim 4
Dependent Claim
47 words
A system in accordance with claim 1 wherein said job processor flush instruction is issued by a processor when the execution of a process by said processor is interrupted for a time period such a to cause such processor to be idle during said interruption time period.
Claim 5
Dependent Claim
30 words
A system in accordance with claim 1 wherein said processor issues said job processor flush instruction when a processor has been executing a processing task for a specified time period.
Claim 6
Dependent Claim
83 words
A system in accordance with claim 1 and further wherein said instruction set further includes a job processor load instruction, a processor being responsive to the issuance of said job processor load instruction for loading the machine state information of a selected processing task from the state block portion corresponding thereto into appropriate locations therefor of said processor to permit said processor to continue the execution, of said selected processing task from the stage of said execution corresponding to said machine state information.
Claim 7
Dependent Claim
90 words
A system in accordance with claim 1 and further wherein said instruction set further includes a job processor fast load instruction, a processor being responsive to the issuance of said job processor fast load instructions for loading only a selected part of the machine state information of a selected processing task from the state block portion corres-ponding thereto into appropriate locations therefor of said pro-cessor to permit said processor to continue the execution of said selected processing task from the stage of said execution corres-ponding to said machine state information.
Claim 8
Dependent Claim
56 words
A system in accordance with claim 6 wherein said pro-cessors each include a plurality of segment base registers con-taining machine state information for forming addresses for use in said processors, and further wherein the selected part of the machine state information loaded into said processor does not include machine state information for said segment base regi-sters.
Claim 9
Dependent Claim
37 words
A system in accordance with claim 1 and further wherein said instruction set further includes a job processor start in-struction, a processor being responsive to a job processor start instruction for initiating the operation of said processor.
Claim 10
Dependent Claim
84 words
A system in accordance with claim 8 wherein a selected one of said plurality of processors is used to control the initia-tion of the operation of all of said processors, said selected processor being responsive to the issuance of a job processor start instruction for initiating its own operation and causing a job processor start instruction for each of the others of said plurality of processors in sequence so that the initiation of the operation of each of said other processors occurs in sequence.
Claim 11
Dependent Claim
38 words
A system in accordance with claim 1 and further wherein said instruction set further includes a job processor stop in-struction, a processor being responsive to a job processor stop instruction for shutting down the operation of said processor.
Claim 12
Dependent Claim
83 words
A system in accordance with claim 10 wherein a selected one of said processors is used to control the shutting down of the operation of all of said processors, said selected processor being responsive to a job processor stop instruction for shutting down its own operation and causing the issuance of a job processor stop instruction for each of the others of said plurality of processors in sequence so that shutting-down of the operation of each of said other processors occurs in sequence.
Claim 13
Dependent Claim
44 words
A system in accordance with claim 1 and further wherein said instruction set further includes a job processor status in-struction, a processor being responsive to the issuance of said job processor status instruction for supplying information con-cerning the status of operation of said processor.
Claim 14
Dependent Claim
31 words
A system in accordance with claim 12 wherein said status information includes an identification of said processor and of the state block corresponding to the process being executed by said processor.
Claim 15
Dependent Claim
49 words
A system in accordance with claim 1 and further wherein said instruction set further includes a job processor load control store instruction, a processor being responsive to the issuance of said job processor load control store instruction for loading control store information into the control store of said processor.
Claim 16
Dependent Claim
225 words
A multiple processor data processing system comprising: a plurality of processors each capable of executing one of a plurality of processing tasks, said processors, when operating, having co-equal status; a common memory the use of which is shared by said plurality of processors, said memory including a data structure having a plurality of state blocks for storing information defining the internal machine states of said processors during the execution of a processing task, each of said state blocks corresponding to one of said plurality of processing tasks; each of said processors operating in response to instructions of an instruction set which set includes a job processor flush instruction; a processor, during the execution of a processing task, being responsive to said job processor flush instruction when the current execution of a processing task by a non-faulty, operating processor is interrupted so that said processor is not able to continue said current execution for a relatively long time period or when a non-faulty, operating processor has been currently executing a processing task for a specified time period, said job processor flush instruction causing the current internal machine state of said processor at the time said processor responds to said job processor flush instruction to be stored into the state block of said data structure which correspond to the processing task being currently executed by said processor.
Claim 17
Dependent Claim
225 words
A multiple processor data processing system comprising: a plurality of processors each capable of executing one of a plurality of processing tasks, said processors, when operating, having co-equal status; a common memory the use of which is shared by said plurality of processors, said memory including a data structure having a plurality of state blocks for storing information defining the internal machine states of said processors during the execution of a processing task, each of said state blocks corresponding to one of said plurality of processing tasks; each of said processors operating in response to instructions of an instruction set which set includes a job processor flush instruction; a processor, during the execution of a processing task, being responsive to said job processor flush instruction when the current execution of a processing task by a non-faulty, operating processor is interrupted so that said processor is not able to continue said current execution for a relatively long time period or when a non-faulty, operating processor has been currently executing a processing task for a specified time period, said job processor flush instruction causing the current internal machine state of said processor at the time said processor responds to said job processor flush instruction to be stored into the state block of said data structure which correspond to the processing task being currently executed by said processor.
Claim 18
Dependent Claim
38 words
A system in accordance with claim 15 wherein the internal machine state of a processor which has responded to a job processor flush instruction is retained in said processor during the execution of said job processor flush instruction.
Claim 19
Dependent Claim
73 words
A system in accordance with claim 15 and further wherein said instruction set further includes a job processor load instruction, a processor being responsive to a job proces-sor load instruction for loading the internal machine state from a state block corresponding to one of said processing tasks into appropriate locations therefor of said processor to permit said processor to said one processing task using the internal machine state loaded from said state block.
Claim 20
Dependent Claim
78 words
A system in accordance with claim 15 and further wherein said instruction set further includes a job processor fast load instruction, a processor being responsive to a fast load instruction for loading only a selected part of the internal machine state from the state block corresponding to one of said processing tasks into appropriate locations there-for of said processor to permit said processor to execute said one processing task using the selection part of the internal machine state.
Claim 21
Dependent Claim
56 words
A system in accordance with claim 18 wherein said processors each include a plurality of segment base registers containing internal machine state information for forming addresses for use in said processors, and further wherein the selected part of the machine state loaded into said processor does not include machine state information for said segment base registers.
Claim 22
Dependent Claim
37 words
A system in accordance with claim 15 and further wherein said instruction set further includes a job processor start instruction, a processor being responsive to a job processor start instruction for initiating the operation of said processor.
Claim 23
Dependent Claim
88 words
A system in accordance with claim 20 wherein during start-up of the system one of said plurality of processors is used to control the initiation of the operation of all of said processors, said one processor being responsive to a job processor start instruction for initiating its own operation and for causing the issuance of a job processor start instruction for each of the others of said plurality of processors in sequence so that the initiation of the operation of each of said other processors occurs in sequence.
Claim 24
Dependent Claim
38 words
A system in accordance with claim 15 and further wherein said instruction set further includes a job processor stop instruction, a processor being responsive to a job processor stop instruction for shutting down the operation of said processor.
Claim 25
Dependent Claim
87 words
A system in accordance with claim 22 wherein during shut-down of the system one of said processors is used to control the shutting down of the operation of all of said processors, said one processor being responsive to the issuance of a job processor stop instruction for shutting down its own operation and for causing a job processor stop instruction for each of the others of said plurality of processors in sequence so that shutting-down of the operation of each of said other processors occurs in sequence.
Claim 26
Dependent Claim
61 words
A system in accordance with claim 15 and further wherein said instruction set further includes a job processor status instruction issued in response to a request from a user with respect to the operating status of a selected processor, said selected processor being responsive to said job processor status instruction for supplying selected information concern-ing the operating status of said processor.
Claim 27
Dependent Claim
33 words
A system in accordance with claim 24 wherein said operating status information includes an identification of said processor and of the state block corresponding to the proces-sing task being executed by said processor.
Claim 28
Dependent Claim
55 words
A system in accordance with claim 15 and further wherein each of said processors has a control store and said instruction set further includes a job processor load control store instruction, a processor being responsive to said job processor load control store instruction for loading control store information into the control store of said processor.
References Cited (Backward Citations)
No citation records indexed.
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