Semiconductor circuit containing integrated bipolar and mos transistors on a chip and method of producing same

Claim 2

In an integrated semiconductor circuit with at least one bipolar transistor and at least one MOS transistor on a chip wherein the contacts from a metal interconnect level to diffused active regions of the bipolar transistor occur over additionally generated interconnects, wherein the improvement comprises: in that emitter and collector contacts of the bipolar transistor as well as the gate electrode of the MOS transistor are composed of the same material which is a silicide of a high melting point metal selected from the group consisting of tantalum, tungsten, molybdenum and titanium.

Claim 3

A method of producing an integrated semiconductor circuit with at least one npn bipolar transistor and at least one p-channel MOS field effect transistor as defined in claim 1, comprising, a sequential combination of the steps: (a) defining an active region of said circuit by producing n+ -doped zones spaced from one another in a p-doped silicon substrate by masked ion implantation; (b) applying an epitaxial n--doped layer on the n+-doped zones; (c) etching an insulation trough in the region between the n+ -doped zones; (d) generating an insulation oxide in the area of the insulation trough, (e) masking remaining portions of the bipolar transistor and areas of the MOS transistor except for the channel region thereof and producing an n+-deep diffusion in a collector region of the bipolar transistor, along with executing a surface-wide channel implantation in the MOS transistor region with n-doping ions; (f) stripping the mask for the deep diffusion collector and for the channel implantation, applying a mask for defining a base zone of the bipolar transistor and executing an ion implantation with p-doping ions for generating the base zone of the bipolar transistor; (g) executing a photo-lithographic process for defining an emitter zone and etching an oxide layer generated on the base zone in the area for the emitter zone; (h) generating the emitter zone by an ion implantation and diffusion of n-doping ions; (i) executing a photo-lithographic process for defining a contact area for the emitter and for defining collector zone areas for the bipolar transistor, as well as gate electrode area for the MOS transistor; (j) depositing surface-wide, a silicide layer and structuring such layer such that it functions as an additional interconnect in the bipolar transistor region and as a gate electrode in the MOS transistor region and functions as an implantation mask in the area of the bipolar transistor during a subsequent base contact implantation and in the area of the MOS transistor during generation of source/drain zones; (k) etching the oxide layer from the bipolar transistor region and the MOS transistor region and executing an ion implantation with p-doping ions for defining a base contact and source/drain zones; (l) annealing the structured silicide layer so as to crystallize the silicide layer while simultaneously electrically activating the implanted ions; (m) depositing an insulation layer functioning as an intermediate oxide; (n) etching contact hole regions for a base contact of the bipolar transistor as well as for the source/drain contacts of the MOS transistor; and (o) metallizing and structuring an outer metal interconnect level.

Claim 4

A method as defined in claim 2, wherein, in step (j), said silicide layer is a silicide of a metal selected from the group consisting of tantalum, titanium, tungsten, and molybdenum.

Claim 5

In a method as defined in claim 2, wherein arsenic ions are utilized for the emitter implantation in step (h) and boron ions are utilized for the base contact implantation as well as for the source/drain implantation in step (k).

Claim 6

A method as defined in claim 2, wherein aluminum is utilized as the metallization for the outer metal interconnect level in step (o).

Claim 7

A method as defined in claim 2, wherein a (100)-oriented, p-doped silicon substrate (1) having a specific resistance in the range of about 10 ohm cm is utilized as the starting substrate.

Claim 8

7, A method as defined in claim 2, wherein the specific resistance of the n--doped epitaxial layer applied in step (d) is in the range of about 2 ohm cm.

Claim 9

A method as defined in claim 2, wherein the silicide layer deposited in step (j) has a layer thickness in the range of about 200 nm.

Claim 10

A method as defined in claim 8, wherein said silicide layer is composed of tantalum silicide.