CA1124834A
Expired / Lapsed
CA
⏱️ 0.0 years remaining
Method of inserting an address signal in a video signal
Assignee: Sony Corp
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Filing: 1981-10-05
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Granted: 1982-06-01
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Expires: 2001-10-05
Abstract
Abstract ABSTRACT OF THE DISCLOSURE Method and apparatus for inserting an address signal in a video signal by compressing the time code signal including synchronizing bits inserted at every predetermined bit and cyclic redundancy check code and then inserting the compressed time code signal into at least one horizontal line period within a vertical blanking period of the video signal. The invention Allows the time code signals to be reconstructed where the record medium is stopped or transported at very low speeds.
Inventors
- 👤 Katsuichi Tachi
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-10-24 00:39
CPC Classifications
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Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
88 words
An apparatus for repro-ducing an address signal from a video signal, comprising: a) means for receiving the video signal including the address signal having a plurality of time code bits corresponding to one field or frame of the video signal and a cyclic redundancy check code; b) means for separating the address signal from the video signal; c) means for storing the time code bits; d) means for checking the address signal; and e) means for generating a read-out pulse based on the output of said checking means.
Claim 2
Independent Claim
88 words
An apparatus for repro-ducing an address signal from a video signal, comprising: a) means for receiving the video signal including the address signal having a plurality of time code bits corresponding to one field or frame of the video signal and a cyclic redundancy check code; b) means for separating the address signal from the video signal; c) means for storing the time code bits; d) means for checking the address signal; and e) means for generating a read-out pulse based on the output of said checking means.
Claim 3
Dependent Claim
22 words
An apparatus as claimed in claim 1, wherein said address signal further includes synchronizing bits inserted at every predetermined number of bits.
Claim 4
Dependent Claim
21 words
An apparatus as claimed in claim 2, further comprising means for correcting time base error based on the synchronizing bits. ?
References Cited (Backward Citations)
No citation records indexed.
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