CA1109967A
Expired / Lapsed
CA
⏱️ 0.0 years remaining
Expandable microprogram memory
Assignee: Bull HN Information Systems Inc
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Filing: 1978-03-20
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Granted: 1981-09-29
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Expires: 1998-03-20
Abstract
Abstract ABSTRACT A method and an apparatus for increasing the capacity and speed of access of a large microprogram control store. The method or apparatus incorporates the use of a 4 bit control field in a microinstruction word which is set into a hardware register to extend the address beyond the normal range of the addressing capability of the microinstruction word. The 4 bits stored in the hardware registers allow 1 of a maximum of 16 read only memory control stores to be selected thereby resulting in the normal addressing circuitry to have a reduced number of components. This technique also allows the selection of another of the memory control stores in one machine cycle.
Inventors
- 👤 Thomas F. Joyce
- 👤 Michel M. Raguin
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-10-27 16:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/0623; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/265; G06F9/267; G06F9/34; G06F9/342
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
199 words
In a data processing system having a plurality of registers for storing electronic signals, at least one read only memory (ROM) having a plurality of banks, each bank for storing a plurality of microprograms each microprogram comprised of a plurality of microwords each microword comprised of a plurality of bits, any of said microwords, stored in said ROM, being ad-dressed by a predetermined number of bits stored in a ROM address register RSAR coupled to said ROM, said data processing apparatus further comprised of a ROM local register (RSLR) also coupled to said ROM for storing any of said microwords, addressed by said predetermined number of bits stored in said ROM address register (RSAR), an apparatus for increasing the capacity and speed of access of said ROM comprising: (a) first means, for storing first coded signals for addressing any one of said plurality of registers; (b) second means, for storing second coded signals of a predeter-mined first constant indicating a predetermined one of said plurality of banks; and (c) third means, coupled to said ROM local register (RSLR) and to said ROM address register RSAP and to said second means for transferring said second coded signals to said RSAF.
Claim 2
Dependent Claim
199 words
In a data processing system having a plurality of registers for storing electronic signals, at least one read only memory (ROM) having a plurality of banks, each bank for storing a plurality of microprograms each microprogram comprised of a plurality of microwords each microword comprised of a plurality of bits, any of said microwords, stored in said ROM, being ad-dressed by a predetermined number of bits stored in a ROM address register RSAR coupled to said ROM, said data processing apparatus further comprised of a ROM local register (RSLR) also coupled to said ROM for storing any of said microwords, addressed by said predetermined number of bits stored in said ROM address register (RSAR), an apparatus for increasing the capacity and speed of access of said ROM comprising: (a) first means, for storing first coded signals for addressing any one of said plurality of registers; (b) second means, for storing second coded signals of a predeter-mined first constant indicating a predetermined one of said plurality of banks; and (c) third means, coupled to said ROM local register (RSLR) and to said ROM address register RSAP and to said second means for transferring said second coded signals to said RSAF.
Claim 3
Dependent Claim
26 words
The apparatus as recited in Claim 1 including fourth means, for storing third coded signals indicative of a second predetermined constant for identifying said first means.
Claim 4
Dependent Claim
33 words
The apparatus as recited in Claim 2 including fifth means coupled to said fourth means, said fifth means being enabled where said fourth means stores coded signals indicative of said second predetermined constant.
Claim 5
Dependent Claim
33 words
The apparatus as recited in Claim 3 including sixth means, coupled to said second means, said sixth means being enabled when said second means stores coded signals indicative of said first predetermined constant.
Claim 6
Dependent Claim
16 words
The apparatus as recited in Claim 3 wherein said fifth means com-prises a first AND gate.
Claim 7
Dependent Claim
16 words
The apparatus as recited in Claim 4 wherein said sixth means com-prises a second AND gate.
Claim 8
Dependent Claim
26 words
The apparatus as recited in Claim 4 including seventh means coupled to said ROM address register (RSAR) for incrementing the contents of said RSAR by one.
References Cited (Backward Citations)
No citation records indexed.
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