CA1103364A
Expired / Lapsed
CA
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Programmable controller with integral microprocessor
Assignee: Allen Bradley Co LLC
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Filing: 1978-01-16
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Granted: 1981-06-16
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Expires: 1998-01-16
Abstract
Abstract PROGRAMMABLE CONTROLLER WITH INTEGRAL MICROPROCESSOR Abstract of the Disclosure An eight-bit microprocessor sequentially reads controller type instructions from a memory and applies the operation codes of selected ones of the instruc-tions to a hardwired Boolean processor. The micro-processor also couples status words between an I/O image table stored in the memory and the I/O interface racks which connect the programmable controller to the machine being controlled. In general, those controller type instructions which are word oriented are executed by the microprocessor and those which are single-bit oriented are executed by the Boolean processor. The Boolean processor is operable in combination with the microprocessor to examine selected status bits in the I/O image table and to set selected status bits therein to a logic state which is deter-mined in part by the state of the examined status bits.
Inventors
- 👤 Raymond A. Grudowski
- 👤 Ernst Dummermuth
- 👤 Valdis Grants
- 👤 Otomar Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-10-31 02:24
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B19/052; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1103; G05B2219/1159; G05B2219/12; G05B2219/1204; G05B2219/13; G05B2219/13128; G05B2219/15; G05B2219/15048; G05B2219/15127
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
301 words
A programmable controller comprising: a random access memory which stores a plurality of macro-instructions which comprise a control program, each of said macro-instructions including a selected one of a plurality of types of opera-tion codes; a read-only memory which stores a first set of machine in-structions which comprise a macro-instruction decoding routine, and a plurality of sets of machine instructions which comprise macro-instruction execution routines, there being a unique macro-instruction execution routine associated with each type of macro-instruction operation code; an address bus connected to said random access memory and said read-only memory to select a line therein; a data bus connected to said random access memory to couple data to and from said random access memory and connected to said read-only memory to couple data from said read-only memory; an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the data bus to sensing devices and operating devices on a machine to be controlled; and a microprocessor for executing machine instructions, said microprocessor being connected to said data bus and said address bus and having a program counter which stores the memory address of a machine instruction stored in said read-only memory and a stack pointer register which stores the address of a macro-instruction stored in said random access memory, said microprocessor being responsive to selected machine instructions in said macro-instruction decoding routine to read out of said random access memory the macro-instruction addressed by said stack pointer register and being res-ponsive to further selected machine instructions in said macro-instruction decoding routine and the operation code in the macro-instruction read from said random access memory to load the start-ing address of the macro-instruction execution routine which is as-sociated with said operation code into said program counter.
Claim 2
Dependent Claim
301 words
A programmable controller comprising: a random access memory which stores a plurality of macro-instructions which comprise a control program, each of said macro-instructions including a selected one of a plurality of types of opera-tion codes; a read-only memory which stores a first set of machine in-structions which comprise a macro-instruction decoding routine, and a plurality of sets of machine instructions which comprise macro-instruction execution routines, there being a unique macro-instruction execution routine associated with each type of macro-instruction operation code; an address bus connected to said random access memory and said read-only memory to select a line therein; a data bus connected to said random access memory to couple data to and from said random access memory and connected to said read-only memory to couple data from said read-only memory; an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the data bus to sensing devices and operating devices on a machine to be controlled; and a microprocessor for executing machine instructions, said microprocessor being connected to said data bus and said address bus and having a program counter which stores the memory address of a machine instruction stored in said read-only memory and a stack pointer register which stores the address of a macro-instruction stored in said random access memory, said microprocessor being responsive to selected machine instructions in said macro-instruction decoding routine to read out of said random access memory the macro-instruction addressed by said stack pointer register and being res-ponsive to further selected machine instructions in said macro-instruction decoding routine and the operation code in the macro-instruction read from said random access memory to load the start-ing address of the macro-instruction execution routine which is as-sociated with said operation code into said program counter.
Claim 3
Dependent Claim
66 words
The programmable controller as recited in claim 1 in which an I/O image table comprised of a plurality of multi-bit status words is stored in said random access memory and in which a macro-instruction execution routine associated with an operation code in one of said macro-instructions includes machine instructions which direct said microprocessor to couple data between said I/O image table and said I/O interface rack.
Claim 4
Dependent Claim
74 words
The programmable controller as recited in claim 1 in which a mapping table comprised of a list of the starting addresses of all the macro-instruction execution routines is stored in said read-only memory and said microprocessor loads the starting address of the macro-instruction execution routine which is associated with said operation code into said program counter by reading it from said mapping table and coupling it through said data bus to said program counter.
Claim 5
Dependent Claim
71 words
The programmable controller as recited in claim 1 in which a Boolean processor is coupled to said microprocessor, said Boolean processor being responsive to selected ones of said macro-instruction operation codes read from said random access memory to perform cor-responding logical operations, and said Boolean processor including means for resetting said microprocessor program counter to the starting address of said macro-instruction decoding routine after said Boolean processor performs its logical operation.
Claim 6
Dependent Claim
278 words
The programmable controller as recited in claim 1 in-cluding a Boolean processor which comprises: a. means coupled to said data bus for decoding selected ones of said operation codes, b. bit selector means having inputs connected to said data bus and being responsive to the bit pointer in selected ones of said control instructions read from said memory to selectively couple the logic state on one of said data bus leads to a bit selector output terminal, c. main decision storage means having an input terminal coupled to said bit selector output terminal, an enable terminal connected to said decoding means and an output terminal, said main decision storage means being res-ponsive to selected decoded operation codes to store a logic state indicative of the logic state of said bit selec-tor output terminal, and d. second bit selector means having an input terminal coupled to said main decision storage means output ter-minal, having a plurality of output terminals coupled to respective leads in said multi-lead data bus, and having an enable terminal coupled to said decoding means, said second bit selector means being responsive to selected decoded operation codes and their associated bit pointer to couple the logic state of said main decision storage means to a selected one of said data bus leads; and in which said Boolean processor includes gate means having one input coupled to said main decision storage means, a second input coupled to said microprocessor, and an output terminal con-nected to one lead in said data bus, said microprocessor being operable to enable said gate means to couple the logic state of said main decision storage means to said one data bus lead.
Claim 7
Dependent Claim
75 words
The programmable controller as recited in claim 5 in which said Boolean processor includes second gate means having one input terminal coupled to a selected one of said data bus leads, a second input coupled to said processor, and an output coupled to said main decision storage means, said processor being operable to enable said second gate means to couple the logic state of said one data bus lead to said main decision storage means.
References Cited (Backward Citations)
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