CA1075360A
Expired / Lapsed
CA
⏱️ 0.0 years remaining
Digital processor
Assignee: Raytheon Co
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Filing: 1976-03-12
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Granted: 1980-04-08
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Expires: 1996-03-12
Abstract
Abstract Abstract of the Disclosure A digital processor is disclosed which is adapted for use in the guidance and stabilization of a guided missile. The digital processor is adapted to store a predetermined macroprogram and to process signals produced by various elements within the missile in accordance with such stored program thereby to produce control signals for the missile's flight control mechanism. The digital processor includes, in addition to a means for storing the macro-program, a data memory and a microinstruction control memory. This latter memory stores sets of microinstructions, each one of such sets corresponding to one of a number of stored macro-instructions which make up the macroprogram. A register is pro-vided which is adapted selectively to load an addressed micro-instruction or a digital test word serially applied by means external to the missile. In such an arrangement the missile's digital processor may be readily checked out through a relatively simple interface mechanism. Also included in the digital processor is a set of address-able flip/flops adapted to be set or reset by signals both in-ternal to and external to the processor. The state of an addresse one of the set of flip/flops serves as a condition signal used in the execution of various ones of the microinstructions. Means are also provided which are adapted to couple the output of the macroprogram storage means to the address inputs of the data memory thereby enabling retrieval of both an instruction from the macroprogram memory and its corresponding operand from the data memory within a single clock pulse interval. This invention wherein described was made in the course of or under a contract or subcontract thereunder, with the Department of Defense.
Inventors
- 👤 John Terzian
Bibliographic Details
Application Number
—
Jurisdiction
CA
Data Source
google_patents
Last Synchronized
2026-11-09 21:04
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/264; G06F9/265; G05; G05D; G05D1/00; G05D1/12
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
353 words
In a digital processor wherein a macroinstruction memory stores a repertoire of macroinstructionds, each one of such macroinstructions corres-ponding to a set of microinstructions; a microinstruction memory stores sets of such microinstructions; a register means stores a digital control word; a source decoder means couples data from one of a plurality of data sources to an input bus selectively in accordance with the stored digital control word; an arithmetic section processes data on such input bus in accordance with the stored digital control word and passes such processed data to an output bus; and a destination decoder means couples processed data on such output bus to one of a plurality of destinations selectively in accordance with the stored digital word,the improvement comprising: (a) a first input means connected to the microinstruction memory for coupling a selected one of the microinstruc-tions in parallel form to such register means; (b) a second input means for coupling binary signals in serial form from a source external to the processor to the register means; (c) control signal means for enabling such register means to store, selectively in accordance with a control signal, as the stored digital word, either the microinstruction coupled by the first input means or the binary signals coupled by the second input means; (d) a condition selector means, coupled to the register means and to a plurality of binary signal sources; for coupling one of such binary signal sources onto a condition true line selectively in accordance with the stored digital word; and, including gate means, responsive to the binary signal source on the condition true line, for enabling or inhibiting, selectively in accordance with the binary signal on the condition true line, the processed data on the output bus to pass to the selected one of the destinations; and (e) a plurality of flip/flops; a flip/ flop selector having a plurality of inputs coupled to the plurality of flip/ flops; and means for coupling a selected one of such flip/flops through the flip/flop selector to enable such selected one of such flip/flops to serve as one of the plurality of binary signal sources.
Claim 2
Dependent Claim
353 words
In a digital processor wherein a macroinstruction memory stores a repertoire of macroinstructionds, each one of such macroinstructions corres-ponding to a set of microinstructions; a microinstruction memory stores sets of such microinstructions; a register means stores a digital control word; a source decoder means couples data from one of a plurality of data sources to an input bus selectively in accordance with the stored digital control word; an arithmetic section processes data on such input bus in accordance with the stored digital control word and passes such processed data to an output bus; and a destination decoder means couples processed data on such output bus to one of a plurality of destinations selectively in accordance with the stored digital word,the improvement comprising: (a) a first input means connected to the microinstruction memory for coupling a selected one of the microinstruc-tions in parallel form to such register means; (b) a second input means for coupling binary signals in serial form from a source external to the processor to the register means; (c) control signal means for enabling such register means to store, selectively in accordance with a control signal, as the stored digital word, either the microinstruction coupled by the first input means or the binary signals coupled by the second input means; (d) a condition selector means, coupled to the register means and to a plurality of binary signal sources; for coupling one of such binary signal sources onto a condition true line selectively in accordance with the stored digital word; and, including gate means, responsive to the binary signal source on the condition true line, for enabling or inhibiting, selectively in accordance with the binary signal on the condition true line, the processed data on the output bus to pass to the selected one of the destinations; and (e) a plurality of flip/flops; a flip/ flop selector having a plurality of inputs coupled to the plurality of flip/ flops; and means for coupling a selected one of such flip/flops through the flip/flop selector to enable such selected one of such flip/flops to serve as one of the plurality of binary signal sources.
Claim 3
Dependent Claim
124 words
The improvement recited in claim 1 including a data memory; a data memory selector means having a first addressing input coupled to the macroin-struction memory and a second addressing input coupled to one of the plurality of the data sources, such data memory selector means being responsive to a second control signal, for coupling either the data on the first addressing input or the data on the second addressing input selectively in accordance with the second control signal to address such data memory; means, responsive to the stored digital control word, for generating the second control signal; means for coupling input data to such data memory from the output bus; and means for coupling data stored in such data memory to the input bus.
Claim 4
Dependent Claim
265 words
In a digital processor wherein a macroinstruction memory stores a repertoire of macroinstructions, each one of such macroinstructions corres-ponding to a set of microinstructions; a microinstruction memory stores sets of such microinstructions; a register means stores a digital control word; a source decoder means couples data from one of a plurality of data sources to an input bus selectively in accordance with the stored digital control word; an arithmetic section processes data on such input bus in accordance with the stored digital control word and passes such processed data to an output bus; and a destination decoder means couples processed data on such output bus to one of a plurality of destinations selectively in accordance with the stored digital word, the improvement characterized in that such register means com-prises: a condition selector means coupled to the register means and to a plurality of binary signal sources for coupling a selected one of such binary signal sources as a signal onto a condition true line selectively in accordance with the stored digital word; and including gate means, responsive to the signal on the condition true line, for enabling or inhibiting the processed data to pass to the selected one of the destinations selectively in accordance with the signal on the condition true line; a plurality of flip/flops; a flip/ flop selector having a plurality of inputs coupled to the plurality of flip/ flops; and means for coupling a selected one of such flip/flops through the flip/flop selector to enable such selected one of such flip/flops to serve as one of the plurality of binary signal sources.
Claim 5
Dependent Claim
265 words
In a digital processor wherein a macroinstruction memory stores a repertoire of macroinstructions, each one of such macroinstructions corres-ponding to a set of microinstructions; a microinstruction memory stores sets of such microinstructions; a register means stores a digital control word; a source decoder means couples data from one of a plurality of data sources to an input bus selectively in accordance with the stored digital control word; an arithmetic section processes data on such input bus in accordance with the stored digital control word and passes such processed data to an output bus; and a destination decoder means couples processed data on such output bus to one of a plurality of destinations selectively in accordance with the stored digital word, the improvement characterized in that such register means com-prises: a condition selector means coupled to the register means and to a plurality of binary signal sources for coupling a selected one of such binary signal sources as a signal onto a condition true line selectively in accordance with the stored digital word; and including gate means, responsive to the signal on the condition true line, for enabling or inhibiting the processed data to pass to the selected one of the destinations selectively in accordance with the signal on the condition true line; a plurality of flip/flops; a flip/ flop selector having a plurality of inputs coupled to the plurality of flip/ flops; and means for coupling a selected one of such flip/flops through the flip/flop selector to enable such selected one of such flip/flops to serve as one of the plurality of binary signal sources.
Claim 6
Dependent Claim
122 words
The improvement recited in claim 3 including a data memory; a data memory selector means having a first addressing input coupled to the macroin-struction memory and a second addressing input coupled to one of the plurality of data source, such data memory selector means being responsive to a second control signal for coupling either the data on the first addressing input or the data on the second addressing input selectively in accordance with the second control signal to address such data memory; means, responsive to the stored digital word, for generating the second control signal; means for coupling input data to such data memory from the output bus; and means for coupling data stored in such data memory to the input bus.
References Cited (Backward Citations)
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